isppac20 Lattice Semiconductor Corp., isppac20 Datasheet - Page 31

• Manufacturer Part Number: isppac20
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

except that they only affect the contents of the DAC
register. The bit codes for these instructions are shown in
Table 6.
ENCAL (enable calibration) is a Lattice instruction that
enables the start of an auto-calibration sequence. This
operation causes all outputs of the device to go to 0V until
the calibration sequence is completed (see timing speci-
fications). As with the programming instructions above,
calibration does not begin until entry of the Run-Test/Idle
state. The completion of the calibration is not dependent,
however, on any further TAP control. This means the
state of the TAP can be returned immediately to the Test-
Logic-Reset state. The only consideration would be to
not clock the TAP during critical analog operations. The
first several milliseconds of the calibration routine are
consumed waiting for configurations to settle, though,
leaving more than enough time to clock the TAP back to
the Test-Logic-Reset state. The bit code for this instruc-
tion is shown in Table 6.
The last Lattice instruction is UBE (user bulk erase).
Operation of the device is interrupted during UBE, after
which all inputs are disconnected and all outputs driven
to V
gramming can only be selectively done in one direction
(from zeroes to ones). The UBE is used to return all user
bits to a zero state at the same time. A UBE usually
IEEE Standard 1149.1 Interface
COM
(2.5V). To economize internal circuitry, pro-
31
proceeds a PRGUSR operation, otherwise one to zero
changes would not be implemented. It can also be used
to erase all configuration information from a device and
is the default condition of parts shipped from the factory.
The same programming constraints apply to UBE as for
PRGUSR. The bit code for this instruction is shown in
Table 6.
The ADDUSR, BYPASS, EXTEST, IDCODE and
SAMPLE/PRELOAD instructions are all executed in the
Update-IR state. Other instructions: PRGUSR, VERUSR
and UBE are executed upon entry of the Run-Test/Idle
state.
It is recommended that when all serial interface opera-
tions are completed, the TAP controller be reset and left
in the Test-Logic-Reset state (the power-up default) and
the TCK and TMS inputs idled. This will insure the best
analog performance possible by minimizing the effects of
digital logic “feed-through.”
Specifications ispPAC20