wm8918 Wolfson Microelectronics plc, wm8918 Datasheet - Page 90

• Manufacturer Part Number: wm8918
• Description: Ultra Low Power Dac For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

WM8918
w
Table 52 Digital Audio Interface Clock Control
COMPANDING
The WM8918 supports A-law and μ-law companding on both transmit (DMIC) and receive (DAC)
sides as shown in Table 53.
Table 53 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
μ-law (where μ=255 for the U.S. and Japan):
A-law (where A=87.6 for Europe):
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs
of data.
Companding converts 13 bits (μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).
8-bit mode is selected whenever AIFRX_COMP=1 or AIFTX_COMP=1. The use of 8-bit data allows
samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B,
8-bit data words may be transferred consecutively every 8 BCLK cycles.
R27 (1Bh)
Audio
Interface 3
R24 (18h)
Audio
Interface 0
REGISTER
REGISTER
ADDRESS
ADDRESS
F(x) = ln( 1 + μ|x|) / ln( 1 + μ)
F(x) = A|x| / ( 1 + lnA)
F(x) = ( 1 + lnA|x|) / (1 + lnA)
10:0
BIT
BIT
11
3
2
1
0
LRCLK_RATE
AIFTX_COMPMOD
AIFRX_COMPMOD
LRCLK_DIR
AIFRX_COMP
AIFTX_COMP
LABEL
[10:0]
LABEL
E
E
DEFAULT
000_0100
_0000
0
DEFAULT
-1 ≤ x ≤ 1
x ≤ 1/A
1/A ≤ x ≤ 1
0
0
0
0
Audio Interface LRCLK Direction
0 = LRCLK is input
1 = LRCLK is output
LRCLK Rate (Master Mode)
LRCLK clock output = BCLK /
LRCLK_RATE
Integer (LSB = 1)
Valid range: 8 to 2047
AIFTX Companding Enable
0 = Disabled
1 = Enabled
AIFTX Companding Type
0 = μ-law
1 = A-law
AIFRX Companding Enable
0 = Disabled
1 = Enabled
AIFRX Companding Type
0 = μ-law
1 = A-law
PD, Rev 4.0, September 2010
DESCRIPTION
DESCRIPTION
Production Data
90