73m2910l ETC-unknow, 73m2910l Datasheet - Page 4

• Manufacturer Part Number: 73m2910l
• Description: Microcontroller
• Manufacturer: ETC-unknow

Microcontroller
BIT 5
0
1
INTERRUPTS
EXTERNAL INTERRUPT DIRECTION REGISTER (IDIR) SFR ADDRESS 092h
Byte Addressable
Reset State 00h
These bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interrupt
and will also allow the user to directly read the logic level at the pads INT(2:0).
BITS (5:3) INT(2:0)
Bits (5:3) are read only bits that reflect the logic value at the corresponding pin. The value is not affected by
bits (2:0).
BITS (2:0) Interrupt Polarity Control
If the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1, a rising edge will trigger the
interrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high
and the internal pin signal to the timer controls will be inverted.
Bits 6 and 7 will always be read as 0’s.
CLOCK CONTROL REGISTER SFR ADDRESS 0DAh
Byte Addressable
Reset State 00h
These bits determine the behavior at the CLK1OUT and CLK2OUT pins and allow the user to divide the main
internal processor clock frequency by two for power conservation.
BIT 7
Bit 7 is an activity bit. It is cleared by a read of this register. If the activity bit is set it will prevent the
73M2910L from entering sleep mode.
BIT 6
When bit 6 = 1, CLK1OUT will be OSC/1.5 if bit 1 is a 1 and bit 0 is 0.
BIT 5 Master Clock Control
When bit 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. If this bit is a 0, the
processor clock is the same frequency as the oscillator’s.
Activity
BIT 7
BIT 7
0
CLOCK OUT
OSC
OSC/2
(continued)
CTRL1
BIT 6
BIT 6
CLK1
0
MCLK
CTRL
BIT 5
BIT 5
INT@
CLK2EN
BIT 4
BIT 4
INT!
4
CTRL1
CLK2
BIT 3
BIT 3
INT)
CTRL0
INTD2
CLK2
BIT 2
BIT 2
CLK1EN
INTD1
BIT 1
BIT 1
CTRL0
INTD0
CLK1
BIT 0
BIT 0