73m2910l ETC-unknow, 73m2910l Datasheet - Page 17

• Manufacturer Part Number: 73m2910l
• Description: Microcontroller
• Manufacturer: ETC-unknow

73M2910L
Microcontroller
BIT 0 Send Flag
When bit 0 is set, a pattern of 7E will be transmitted to the PTXD output as soon as either the next data byte or
CRC has completed transmission. No 0s will be inserted during the flag transmission. When bit 0 is reset back
to a 0, the HDLC circuitry will complete the flag byte in progress and then transmit according to bits in the TX
Control Register. TX ready interrupts will be generated as each byte of flag transmission is initiated.
HDLC STATUS REGISTER (HSTAT) SFR ADDRESS 0C3h
Byte Addressable
Read Only Register
Reset State 00h
If any of the HDLC status bits are set, bit 1 of the HDLC Interrupt Register (new status) will be set if the
corresponding bit in the HDLC Interrupt Enable Register is set.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INVAL
INVAL
TX
RX
INVAL
ABORT
IDLE
FLAG
CRC32
CRC16
UNDRN
OVRN
FLAG
DET
DET
DET
BIT 7 Invalid CRC 32
Bit 7 will be set if the CRC search mode or the 32-bit CRC is enabled by the HDLC Control Register and an
incorrect remainder for the 32-bit CRC is detected at the last received byte prior to receiving a flag.
Bit 7 will by cleared upon a reset and is cleared by a read of the HDLC Stat Register.
BIT 6 Invalid CRC 16
Bit 6 will be set if the CRC search mode or the 16-bit CRC is enabled by the HDLC Control Register and an
incorrect remainder for the 16-bit CRC is detected at the last received byte prior to receiving a flag.
Bit 6 will by cleared upon a reset and is cleared by a read of the HDLC Stat Register.
BIT 5 TX Underrun
When Bit 5 is set, a transmit underrun condition has been detected. This is a condition where the HDLC has
finished transmitting a message byte, but no new data has been loaded into the TX Data Register, and no other
transmit control bit has been set. This bit will be set only if the send data bit, bit 1 of the TX Control Register is
set. The transmit data is double buffered since the TX Data Register is downloaded into a TX Serial Register
when the HDLC begins to transmit a new data byte. At the time of loading the TX Serial Register, a TX ready
interrupt is generated. This interrupt must be serviced by either loading a new data byte (the next data byte to
be transmitted) into the TX Data Register, or by setting another TX control bit, before the current data byte has
completed transmission (at which point another TX ready interrupt would be generated). If a TX underrun is
detected, the HDLC will abort the current transmission by sending continuous ones and will reset the send data
control bit in the TX Control Register.
Bit 5 will by cleared upon a reset and is cleared by a read of the HDLC Stat Register.
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