sc16c752-04 NXP Semiconductors, sc16c752-04 Datasheet
sc16c752-04
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sc16c752-04 Summary of contents
Page 1
... The SC16C752 is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates Mbits/s (3.3 V and 5 V). The SC16C752 offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access ...
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... Product data 8-bit characters Even, odd parity bit generation and detection 1, 1. stop bit generation Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO Version 7 1.4 mm SOT313-2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... FIFO REGISTER REGISTER RECEIVE FIFO REGISTER REGISTER CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO TXA, TXB SHIFT RECEIVE RXA, RXB SHIFT DTRA, DTRB RTSA, RTSB OPA, OPB MODEM CONTROL LOGIC CTSA, CTSB ...
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... Chip Select (Active-LOW). These pins enable data transfers between the user CPU and the SC16C752 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic LOW on the respective CSA and CSB pins. Rev. 04 — 20 June 2003 ...
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... Data Terminal Ready (Active-LOW). These outputs are associated with individual UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC16C752 is powered-on and ready. These pins can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem ...
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... RX FIFO is empty. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C752. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Transmit Ready (Active-LOW). TXRDYA or TXRDYB go LOW when there are at least a trigger level number of spaces available or when the FIFO is empty ...
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... Philips Semiconductors The SC16C752 has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters ...
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... Product data 3). Figure 4 shows RTS functional timing. The receiver FIFO STOP START BYTE STOP 1 2 BYTE 0-7 STOP Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO Figure 1 “Block START N N+1 002aaa226 Section 6.2.1. START BYTE 0-7 STOP 002aaa227 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO. 6.3.1 RX When software flow control operation is enabled, the SC16C752 will compare incoming data with Xoff1,2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character are received, transmission is halted after completing transmission of the current character ...
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... Xon-2 WORD Xoff-1 WORD COMPARE Xoff-2 WORD PROGRAMMED Xon-Xoff CHARACTERS UART1 is transmitting a large text file to UART2. Both UARTs are Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO UART2 RECEIVE FIFO SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon-1 WORD Xon-2 WORD Xoff-1 WORD ...
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... Signal RESET functions Reset control RESET RESET RESET RESET RESET Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO st character while Reset state All bits cleared. Bit 0 is set. All other bits cleared. All bits cleared. Reset to 00011101 (1D hex). ...
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... Philips Semiconductors 6.5 Interrupts The SC16C752 has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5 ...
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... Fig 8. FIFO polled mode operation. 9397 750 11635 Product data Figure 7 shows interrupt mode operation. IOW / IOR INT PROCESSOR IOW / IOR PROCESSOR Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO IIR IER THR RHR 002aaa230 Figure 8 ...
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... LOCATION FILLED TXRDY FIFO EMPTY When empty, the TXRDY signal becomes active. TXRDY will go inactive RXRDY is active when there is at least one character in the FIFO. It Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO RX RXRDY rdptr AT LEAST ONE LOCATION FILLED ...
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... It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7]. 6.7 Sleep mode Sleep mode is an enhanced feature of the SC16C752 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • ...
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... When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. 6.9 Programmable baud rate generator The SC16C752 UART contains a programmable baud generator that takes any clock input and divides divisor in the range between 1 and (2 divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in ...
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... Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO Percent error difference between desired and actual 0.026 0.058 0.69 2.86 Percent error difference between desired and actual 0.026 0.034 0.312 0.628 1.23 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... FIFO ready register Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO 1 1.8432 MHz 002aaa169 Write mode transmit holding register (THR) interrupt enable register ...
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... These registers are accessible only when LCR[ [2] The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled. 9397 750 11635 Product data lists and describes the SC16C752 internal registers. Bit 5 Bit 4 Bit 3 bit 5 ...
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... TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs. 9397 750 11635 Product data Table 9 for more register access information. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO ’. Hex © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... FIFO. FCR[0] FIFO enable. Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Word length bits 1, 0. These two bits specify the word length to be transmitted or received bits bits bits bits Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Logic 1 = Overrun error has occurred. LSR[0] Data in receiver. Logic data in receive FIFO (normal default condition). Logic least one character in the RX FIFO. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... RTS output is controlled by hardware flow control. MCR[0] DTR Logic 0 = Force DTR output to inactive (HIGH). Logic 1 = Force DTR output to active (LOW). In loop-back mode, controls MSR[5]. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Logic 1 = Enable the RTS interrupt. [1] IER[5] Xoff interrupt. Logic 0 = Disable the Xoff interrupt (normal default condition). Logic 1 = Enable the Xoff interrupt. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO Table 15 shows modem status © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... IIR[3:1] 3-bit encoded interrupt. See IIR[0] Interrupt status. Logic interrupt is pending. Logic interrupt is pending. Table Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO …continued Section 6.7 “Sleep mode” for details. Table 18. 18. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... MCR[7:5] can be modified, i.e., this bit is therefore a write enable. EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 3 “Software flow control options (EFR[0:3])” on page 9. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO IIR[1] IIR[0] Source of the interrupt 1 0 Receiver Line Status error ...
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... The TLR should be programmed for where N is the desired trigger level. When the trigger level setting in TLR is zero, the SC16C752 uses the trigger level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level defi ...
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... FIFO Rdy[4] RX FIFO A status. Related to DMA. FIFO Rdy[3:2] Unused; always 0. FIFO Rdy[1] TX FIFO B status. Related to DMA. FIFO Rdy[0] TX FIFO A status. Related to DMA. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Set MCR (04 temp3 Set TCR (06) to VALUE Set MCR (04) to temp3 Set LCR (03 Set EFR (02) to temp2 Set LCR (03) to temp1 Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Set prescaler value to divide-by-4 [1] 9397 750 11635 Product data Register programming guide sign here means bit-AND. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO …continued Actions Read LCR (03), save in temp1 Set LCR (03 Read EFR (02), save in temp2 Set EFR (02 temp2 ...
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... V on non-hysteresis inputs. IH(max) Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO Min Max - 7 0 0 +85 65 +150 3.3 V and 5 V Min Nom Max + 10 2.0 - ...
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... Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO 3.3 V and 5 V Unit Max Min Max - 100 ...
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... Conditions Min 10 [3] - 200 [2] 30 VALID t h4 ACTIVE ACTIVE DATA Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO 2.5 V 3.3 V and 5 V Unit Max Min Max - MHz - 200 - ...
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... Fig 15. Alternate read/write strobe timing. 9397 750 11635 Product data VALID t h4 ACTIVE ACTIVE t su2 t h3 DATA t d19 t h5 Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO 002aaa236 002aaa237 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Fig 16. Modem input/output timing. 9397 750 11635 Product data t d7 CHANGE OF STATE CHANGE OF STATE t d8 ACTIVE t d9 ACTIVE Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO CHANGE OF STATE t d8 ACTIVE ACTIVE ACTIVE ACTIVE t d8 CHANGE OF STATE 002aaa238 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Product data DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT d10 ACTIVE t d11 ...
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... Fig 19. Receive ready timing in FIFO mode. 9397 750 11635 Product data DATA BITS (5- DATA BITS (5- Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT d15 ACTIVE DATA READY t d16 ACTIVE ...
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... Product data DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY 16 BAUD RATE CLOCK Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT d14 ACTIVE 002aaa242 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Fig 21. Transmit ready timing in non-FIFO mode. 9397 750 11635 Product data DATA BITS (5- d17 ACTIVE TRANSMITTER READY Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT d18 TRANSMITTER ...
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... Product data DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t d18 TRIGGER LEAD Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO PARITY STOP BIT BIT D6 D7 002aaa244 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... 2 scale (1) ( 0.18 7.1 7.1 9.15 9.15 1 0.5 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO SOT313 detail X (1) ( 0.75 0.95 0.95 7 0.2 0.12 0.1 o 0.45 0.55 0.55 0 EUROPEAN ...
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... Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 9397 750 11635 Product data 2.5 mm thick/large packages. Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , [5] , SO, SOJ Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO Soldering method Wave Reflow not suitable suitable [4] not suitable suitable ...
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... Product data (9397 750 09575); ECN 853-2379 28891 of 10 September 2002. 9397 750 11635 Product data 10 C measured in the atmosphere of the reflow 18: capacitors’ values changed and Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Rev. 04 — 20 June 2003 SC16C752 Dual UART with 64-byte FIFO Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 June 2003 Document order number: 9397 750 11635 SC16C752 Dual UART with 64-byte FIFO 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32 10 Static characteristics ...