xr16l2550im Exar Corporation, xr16l2550im Datasheet - Page 26

• Manufacturer Part Number: xr16l2550im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
•
•
4.6
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Line Control Register (LCR) - Read/Write
Table 11
BIT-2
FCR B
0
1
1
0
0
1
1
T
for parity selection summary below.
ABLE
IT
-7
BIT-1
0
0
1
1
10: R
W
ORD LENGTH
5,6,7,8
FCR B
6,7,8
ECEIVE
5
0
1
0
1
BIT-0
IT
-6
0
1
0
1
FIFO T
26
1 (default)
R
T
RIGGER
L
RIGGER
ECEIVE
EVEL
14
4
8
S
TOP BIT LENGTH
W
ORD LENGTH
5 (default)
L
EVEL
Table 10
16C550, 16C2550,
16C2552, 16C554,
16C580 compatible.
6
7
8
1 (default)
S
1-1/2
C
ELECTION
2
OMPATIBILITY
(B
shows the complete selections.
IT TIME
(
S
))
REV. 1.1.2