xr16l2550im Exar Corporation, xr16l2550im Datasheet - Page 22

• Manufacturer Part Number: xr16l2550im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
SEE”RECEIVER” ON PAGE 12.
SEE”TRANSMITTER” ON PAGE 11.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2550 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates Transmit FIFO is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
4.3.2
A
A2-A0
DDRESS
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
IER versus Receive/Transmit FIFO Polled Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
XON1 RD/WR
XON2 RD/WR
N
EFR
R
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
R
W
EAD
RITE
/
Enable
B
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
-7
Enable
B
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RTS
IT
-6
Enhanced Registers
Special
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
IT
-5
22
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Enable
B
Bit-4
Bit-4
Bit-4
Bit-4
IT
-4
S
HADED BITS ARE ENABLED WHEN
B
ware
Soft-
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
-3
B
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
-2
B
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
-1
B
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
EFR B
IT
-0
IT
LCR=0
-4=1
C
OMMENT
REV. 1.1.2
X
BF