ak4368 AKM Semiconductor, Inc., ak4368 Datasheet - Page 24

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ak4368

Manufacturer Part Number
ak4368
Description
Dac With Built-in Pll & Hp-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet
ROTM1
0
0
1
1
ASAHI KASEI
The ALC (Automatic Level Control) is controlled by the ALC block when ALC bit is “1”. When ALC bit = “0”, the gain
of ALC block is fixed to 0dB.
[1] ALC Limiter Operation
During ALC limiter operation, when either the left or right channel exceeds the ALC limiter detection level (−6.0dBFS),
the volume of both channel (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step
(LMAT1-0 bits, Table 13). The volume is changed by the ALC limiter operation at the individual zero crossing points of
the left and right channels, or at the zero crossing timeout. ROTM1-0 bits set the zero crossing timeout period of both the
ALC limiter and recovery operation (Table 12). Then the volume is set to the same value for both channels.
MS0529-E-00
ALC Operation
ROTM0
0
1
0
1
LMAT1
0
0
1
1
Table 12. ALC Recovery Operation Waiting Period, Zero Crossing Timeout Period
Reserved
1024/fs
2048/fs
4096/fs
LMAT0
0
1
0
1
ALC Recovery Operation Waiting Period, Zero Crossing Timeout Period
fs=16kHz
128ms
256ms
64ms
-
ALC Output ≥
−6.0dBFS
1
2
2
2
Table 13. ALC Limiter ATT Step
fs=22.05kHz
186ms
46ms
93ms
-
ALC Output ≥
0dBFS
ALC Limiter ATT Step
1
2
2
4
- 24 -
fs=24kHz
171ms
43ms
85ms
-
ALC Output ≥
+6dBFS
fs=32kHz
1
2
4
4
128ms
32ms
64ms
-
ALC Output ≥
+12dBFS
fs=44.1kHz
23ms
46ms
93ms
1
2
4
8
-
Default
fs=48kHz
21ms
43ms
85ms
[AK4368EG]
-
2006/07
Default

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