ald523d Advanced Linear Devices Inc (ALD), ald523d Datasheet - Page 6

• Manufacturer Part Number: ald523d
• Description: Multifunction 7-digit Serial Input Display Module Controller
• Manufacturer: Advanced Linear Devices Inc (ALD)

polarity and the serial clock SCLK polarity can be
inverted, as described in the next section.
The positions of the serial data bits and sign bit within a
given serial data word are determined by the 32 bit data bit
mask register “SMSK1” to “SMSK4” and the 32 bit sign
bit mask register “SMSK5” to “SMSK8” parameters in the
.CDS file. Bit masking rules are as follows:
1. Maximum serial word length that the ALD523D can
2. Maximum serial data bits that the ALD523D can
3. Minimum serial data bits that the ALD523D can
4. The input serial data bits must be in a consecutive
5. The sign bit can be anywhere outside the serial data
BIT AND SIGN MASKING
Bit masking is set by the user by programming SMSK1
through SMSK4 from memory address 60H to 63H.
SMSK1 indicates the position of the first 8 bits of a 32-bit
serial data word mask. SMSK2, SMSK3 and SMSK4
indicates the position of the next 24 bits of the 32-bit serial
data word mask, respectively. Initially, all 32 bits are set
to 0. When the last “1” bit is set anywhere within the 32
bit serial data word, it sets the LSB bit position. The “1”
bit starts at MSB, followed by “1” bits, until the LSB bit
is reached. After the LSB bit, any subsequent bit must be
left as “0” bits. The number of “1” bits between MSB bit
and the LSB bit determines the length of the serial data
word.
technique. In this example, there are 23 SCLK clock
cycles, a sign bit and a 16 bit data word. SCLK clock starts
at bit 7 of SMSK2. MSB starts on the 4
ALD523D
Table 1 illustrates an example of the serial bit masking
Hexadecimal
© © © © 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: [phone], Fax: [phone]
Binary
receive are 32 bits in 32 SCLK clock cycles. One of
the serial bits can be optionally a sign bit. If a serial
word has less than 32 bits, the last clock of the SCLK
clock stream when DVCS goes from a “0” to a “1”
stops the data word counter.
process are 21 bits plus 1 sign bit for a total of 22 bits.
process are 2 bits, including a sign bit. The number of
clock cycles between when DVCS goes from “1” to
“0” to when DVCS goes from “0” to “1” defines the
total input serial word length, right justified, from bit
0 of the 32 bit input mask register.
order, from MSB bit first to LSB bit last.
bits stream but within the serial data word.
Table 1. Serial data bit masking technique
bit31
00000000
SMSK1
Byte-1
00
12/01
00001111
SMSK2
Byte-2
0F
11111111
SMSK3
Byte-3
th
FF
clock cycle, or
.
11110000
http://www.aldinc.com
SMSK4
Byte-4
F0
bit0
bit 4 of SMSK2, of the serial data stream. Data is being
continuously clocked into the ALD523D until the 23
clock cycle or until DVCS goes from “0” to “1”. The LSB
of the data word is positioned at the 19
length of the serial word is determined by the number of
consecutive “1” in the masking bits, which is 16 bits.
Sign masking is set by the user by programming SMSK5
through SMSK8 from memory address map 64H to 67H.
Initially, all 32 bits from SMSK5 to SMSK8 are set to 0.
A “1” bit anywhere between SMSK5 through SMSK8
indicates the position where the sign information is
located. There can only be one “1” bit within the 32-bit
serial data stream, situated outside the serial data bit
stream, and all remaining bits must be “0” bits. In this
example, the data word has 23 clock cycles.
Table 2 illustrates the example of sign bit masking
technique. The sign bit data is available on the first clock
cycle of the 23-bit data word stream. In this example,
placing a “1” anywhere between the fourth bit of SMSK6,
through all the bits of SMSK7, until the fifth bit of
SMSK8, corresponding to between the 4
the 19
is also valid for any number of SCLK, between 23 and 32,
of the input data word, while DVCS is low.
In default mode, the sign bit is defined by logic “0” as a
positive sign, and logic “1” as a negative sign, and the
serial clock is SCLK. As an option, the sign bit and the
serial clock polarity can be inverted by setting “Mx” equal
to “D” (HEX) instead of “C” (HEX). The serial clock now
becomes SCLK, and the sign bit polarity is defined as
logic “1” for a positive sign, and logic “0” for a negative
sign (see Table 1 of the ALD523D Setup and Calibration
Software User Guide).
SELECTING AND CONFIGURING DISPLAY LINE
WITH FREQUENCY MODE AND INPUT CLOCK
DIVIDER
The ALD523D is designed to be compatible with industry
standard 1-line x 16-character and 2-line x 16-character
CDM, and to operate under different input frequencies of
the clock source. This feature is programmable through
the “SETF” parameter in the .CDS file.
parameter is a 4-bit hexadecimal number (0-B) located on
the first line of the .CDS file, and corresponds to address
00H of the EEPROM.
Hexadecimal
Binary
th
SCLK clock cycle, is not allowed. This example
Table 2. Sign bit masking technique
bit31
00000000
SMSK5
Byte-5
00
01000000
SMSK6
Byte-6
40
00000000
th
SMSK7
Byte-7
th
clock cycle. The
00
clock cycle to
The “SETF”
.
00000000
6 of 20
SMSK8
Byte-8
00
bit0
rd