ald523d Advanced Linear Devices Inc (ALD), ald523d Datasheet - Page 16

• Manufacturer Part Number: ald523d
• Description: Multifunction 7-digit Serial Input Display Module Controller
• Manufacturer: Advanced Linear Devices Inc (ALD)

TIMING CHARACTERISTICS
T
Display Only (Mode-C) Timing
DATIN Setup Time
Serial Clock Low Time
Serial Clock High Time
DVCS to DATIN Valid Time
Serial Clock to DVCS High Time
Power Timing
Power-On-Reset Time
Data Transfer From PC Timing
Calibration to Data Valid Time
Serial Clock High Time
Serial Clock Low Time
Data Valid to Serial Clock Delay Time
Serial Clock to Data Valid High Time
Serial Clock to Data Valid Low Time
DATIN Setup Time
Data Valid High Time
Serial Clock to Calibration Time
Reference Calibration Timing
Auto Zero Time
Integration Time
Integrator Zero Time
Calibration Setup Time
Calibration Delay Time
DATOUT Valid Setup Time
DATOUT Not Valid Time
DATOUT Valid Time
DATOUT Valid Time Out Time
DATOUT Out Time
Input / Output Characteristic Timing
Input Interrupt Low Time
Rise/Fall Times (CL = 10pF)
Oscillator (OSC
Crystal Frequency
External Frequency (OSC
1
2
3
4
5
ALD523D
Extendible from S1, S2, and S3 hardware switches through “SETF” parameter in the .CDS file. Lower integration time than the
minimum allows more conversion cycles per second at reduced count resolution. Higher integration time increases count resolution,
but requires increased capacitor value and lowered number of conversion cycles per second. De-integration time depends on
selection of full scale input range, integration capacitor value and voltage reference.
device, and may affect device reliability and performance.
operation, t
Apply only for calibrated reference (mode-A) and ratiometric (mode-B) operations.
ESD Sensitive Device. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
PC to ALD523D handshake using page write mode.
Calibration delay time (t
A
© © © © 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: [phone], Fax: [phone]
= 0
o
C - 70
CD
o
must be for a minimum of one complete conversion cycle to assure synchronization to start of auto zero phase cycle time.
Parameter
C, V
IN
1, 2
, OSC
+
= +5V, f
12/01
CD
5
OUT
) may be as short as 7 µs, if start of auto zero phase cycle time could be determined. For asynchronous
IN
)
)
XTL
4
= 3.6864 MHz, internal system clock = f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
Symbol
DS
SCL
SCH
DIV
DVCSH
POR
CALDV
SCLKH
SCLKL
DSdelay
SCDVH
SCDVL
DS
DVH
SCCAL
AZ
INT
INTZ
CS
CD
DVS
DNV
DV
TO
DATOUT
IL
R
XTL
OSC
, t
F
http://www.aldinc.com
3.7
16.2
67.6
67.62
10
0.271
0
0
2.4
10
0
16.667
1.1
1
18
11
70
Min
2
t
2
15
25
3.6864
INT
Typ
22.22
1.9
67
500,000
DC
DC
8
300
5.5
500
125
8
8
XTL
Max
/4 unless otherwise specified
Conv. Cycle
MHz
MHz
Unit
sec
ms
ms
ms
ms
ms
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
CAL, PWRCS, COUT, DVCS
Rise time/Fall time ≤ 15 ns
Test Conditions
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