ald523d Advanced Linear Devices Inc (ALD), ald523d Datasheet - Page 11

• Manufacturer Part Number: ald523d
• Description: Multifunction 7-digit Serial Input Display Module Controller
• Manufacturer: Advanced Linear Devices Inc (ALD)

three modes of operations, DSA1 and DSA2 pins on the
ALD523D function as data sample averaging selection
switches. Four DSA1 and DSA2 switch combinations are
described in Table 7.
selects a pre-defined averaging/sampling.
When DSA1=0 and DSA2=0, the ALD523D is set to non-
averaging mode.
ALD523D utilizes the “AVG1” parameter set at address
02H of the EEPROM memory. At DSA1=0 and DSA2=1,
the ALD523D utilizes “AVG2” at address 03H of the
EEPROM. At DSA1=1 and DSA2=1, the ALD523D
utilizes “AVG3” at address 04H of the EEPROM.
hexadecimal numbers at addresses 02H, 03H, and 04H of
the first line of the .CDS file, respectively. Valid “AVG1”,
“AVG2” and “AVG3” values are 1, 2, 4, 8, 16, 32, 64, and
128. These values correspond to the number of data
samples averaged.
ALD523D
“AVG1”, “AVG2”, and “AVG3” parameters are 8-bit
Table 7. Averaging selection switch combination for mode-
GROUP
FUNCTION
PIN
SWITCHES
LOGIC LEVEL
GROUP
FUNCTION
PIN
SWITCHES
LOGIC LEVEL
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A, mode-B, and mode-C
DSA1
S1
6
0
1
0
1
3
0
0
0
0
1
1
1
1
At DSA1=1 and DSA2=0, the
12/01
Table 8. Integration time selection switch combination for mode-A and mode-B
DATA SAMPLE AVERAGING
Each logical state combination
DSA2
7
0
0
1
1
27
S2
.
0
0
1
1
0
0
1
1
(1, 2, 4, 8, 16, 32, 64, 128)
(1, 2, 4, 8, 16, 32, 64, 128)
(1, 2, 4, 8, 16, 32, 64, 128)
J4
28
S3
0
1
0
1
0
1
0
1
AVERAGE
No Average
AVG1
AVG2
AVG3
(1)
INTEGRATION TIME
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100.000 ms
166.667 ms
200.000 ms
300.000 ms
INTEGRATION TIME SELECTION
16.667 ms
33.333 ms
50.000 ms
66.667 ms
SELECTING AND CONFIGURING INTEGRATION
TIME
When ALD500/ALD500R and ALD523D are used
together as a chip set, an integration time needs to be
selected for the system. For maximum 50/60-cycle line
power noise rejection, Integration time t
as a multiple of the period of the power line frequency.
For example, t
50.000msec,
200msec, and 300msec maximize 60Hz power line noise
rejection.
300msec maximize 50Hz power line noise rejection.
In general, the longer the integration time, the better the
noise rejection of the power line noise, but it also takes
longer to complete a conversion cycle.
recommended integration time of 100msec offers the best
tradeoff of noise performance, conversion time and both
50/60-cycle power line noise rejection.
integration time also offers the benefit of being universally
optimal for both 50 and 60 cycles power line noise
rejection.
The ALD523D utilizes S1, S2, and S3 as control-input
pins for selecting different integration times. In mode-A
and mode-B, these switches set different integration time
for different measurement needs based on different R
and C
sheet for more information). However, these three pins
are disabled in mode-C operation. The S1, S2 and S3
logical state combinations are listed in Table 8.
J5
APPRX. CONVERSION / SEC
Int
time constant values (see ALD500/ALD500R data
The t
66.667msec,
INT
6.6
1.5
10
5
4
3
2
1
INT
times of 16.667msec, 33.333msec,
times of 100msec, 200msec, and
100msec,
.
NO. OF 60 Hz CYCLES
INT
must be picked
The 100msec
10
12
18
1
2
3
4
6
166.67msec,
11 of 20
Default
Int