tc59lm818dmbi TOSHIBA Semiconductor CORPORATION, tc59lm818dmbi Datasheet - Page 42

• Manufacturer Part Number: tc59lm818dmbi
• Description: 288mbits Network Fcram2 I-version ? 4,194,304-words ? 4 Banks ? 18-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

MODE REGISTER SET TIMING (CL = 4, BL = 2)
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
From Read operation to Mode Register Set operation.
Command
BA0, BA1
A14~A0
(output)
(output)
(output)
(output)
(input)
(input)
CLK
CLK
QS
DQ
DQ
QS
DS
DS
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
RDA
UA
BA
0
Low
LAL
LA
1
2
CL + BL/2
3
DESL
4
5
Q0 Q1
Q0 Q1
RDA
6
(opcode)
BA0="0"
BA1="0"
MRS
Valid
7
8
9
I
RSC
10
DESL
= 7 cycles
TC59LM818DMBI-37
11
2005-03-07 42/55
12
13
WRA
RDA
Rev 1.2
UA
BA
14
or
LAL
LA
15