tc59lm818dmbi TOSHIBA Semiconductor CORPORATION, tc59lm818dmbi Datasheet - Page 41

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tc59lm818dmbi

Manufacturer Part Number
tc59lm818dmbi
Description
288mbits Network Fcram2 I-version ? 4,194,304-words ? 4 Banks ? 18-bits
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
Unidirectional DS/QS mode
Command
Unidirectional DS/Free Running QS mode
Address
(output)
(output)
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
(input)
(input)
(input)
(input)
CLK
PD
CLK
DQ
DQ
QS
QS
DS
DS
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
RDA
UA
0
Low
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
PD should be brought to "High" within t
LAL
LA
1
WL = 3
WL = 3
2
3
D0 D1 D2 D3
D0 D1 D2 D3
4
5
DESL
REFI
t
6
QPDH
(max.) to maintain the data written into cell.
t
IH
7
t
IS
8
I
PD
= 2 cycle
9
l
RC(min)
10
, t
REFI(max)
PDA
n-2
TC59LM818DMBI-37
cycles later.
n-1
2005-03-07 41/55
n
DESL
n+1
Rev 1.2
I
t
PDA
PDEX
n+2
WRA
RDA
UA
or

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