lf3321qc9 LOGIC Devices Incorporated, lf3321qc9 Datasheet - Page 14

• Manufacturer Part Number: lf3321qc9
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LF Interface
Continued
LOGIC Devices Incorporated
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Functional Description
Table 19 shows an example of loading data into Filter B limit register 7. Data value 3B60H is loaded as
the lower limit and 72A4H is loaded as the upper limit. It takes 9S clock cycles to load S coefficient sets
into the device. Therefore, it takes 2304 clock cycles to load all 256 coefficient sets. Assuming an 83 MHz
clock rate, all 256 coefficient sets can be updated in less than 27.7 µs, which is well within vertical blanking
time. It takes 5S clock cycles to load S round or limit registers. Therefore, it takes 320 clock cycles to
update all round and limit registers (both Filters A and B). Assuming an 83 MHz clock rate, all Filter A and B
round/limit registers can be updated in 3.84 µs.
The coefficient banks and Configuration/Control registers are not loaded with data until all data values for
the specified address are loaded into the LF Interface
to until all eight coefficients have been loaded into the LF Interface
until all four data values are loaded.
After the last data value is loaded, the interface will expect a new address value on the next clock cycle.
After the next address value is loaded, data loading will begin again as previously discussed. As long
as data is loaded into the interface, LDA must remain LOW. After all desired coefficient banks and
Configuration/Control registers are loaded with data, the LF Interface
setting LDA HIGH on the clock cycle after the clock cycle which latches the last data value. It is important
that the LF Interface
The Filter A coefficient banks may only be loaded with the Filter A LF Interface
banks may only be loaded with the Filter B LF Interface
loaded with either the Filter A or B LF Interfaces
Since both LF Interfaces
respective coefficient banks at the same time. Or, one LF Interface
registers while the other loads it’s respective coefficient banks. If both LF Interfaces
Configuration or Control register at the same time, the Filter B LF Interface
Filter A LF Interface
register at the same time that the Filter B LF Interface
Filter B LF Interface
be allowed to load the configuration register. However, the Filter A LF Interface
as if the write occurred.
PAUSEA/PAUSEB
CFA/CFB
Figure 14. Limit Register Loading Sequence with PAUSE Implementation
LDA/LDB
CLK
11-0
W1: Limit Register loaded with new data on this rising clock edge.
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ADDR
. For example, if the Filter A LF Interface
will be allowed to load the round register while the Filter A LF Interface
remain disabled when not loading data into it.
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1
operate independently of each other, both LF Interfaces
DATA
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1
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.
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LIMIT REGISTER
. In other words, the coefficient banks are not written
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DATA
attempts to load a Filter A round register, the
. The Configuration and Control registers may be
2
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attempts to load data into a configuration
Horizontal Digital Image Filter
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. A round register is not written to
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can load the Configuration/Control
must be disabled. This is done by
DATA
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Improved Performance
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will be given priority over the
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Video Imaging Products
and the Filter B coefficient
will continue to function
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can load data into their
are used to load a
DATA
Feb 5, 2003 LDS.3321-A
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4
will not
LF3321
W1