ata5773 ATMEL Corporation, ata5773 Datasheet - Page 175

• Manufacturer Part Number: ata5773
• Description: Microcontroller With Uhf Ask/fsk Transmitter
• Manufacturer: ATMEL Corporation

14.3.5
14.3.6
14.4
14.4.1
14.4.2
14.4.3
8006G–AVR–01/08
Alternative USI Usage
Start Condition Detector
Clock speed considerations
Half-Duplex Asynchronous Data Transfer
4-Bit Counter
12-Bit Timer/Counter
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by forcing the
acknowledge bit low after the last byte transmitted.
The start condition detector is shown in
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in two-wire mode.
Figure 14-6. Start Condition Detector, Logic Diagram
The start condition detector is working asynchronously and can therefore wake up the processor
from power-down sleep mode. However, the protocol used might have restrictions on the SCL
hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses,
see
Refer to the description of the USISIF bit on
Maximum frequency for SCL and SCK is f
receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-
trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the
actual data rate in two-wire mode.
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
Using the USI Data Register in three-wire mode it is possible to implement a more compact and
higher performance UART than by software, only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will increment the counter value.
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
“Clock Systems and their Distribution” on page
enables its output. If the bit is set, a master read operation is in progress (i.e., the slave
drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
given by the master (F), or a new start condition is given.
Write( USISIF)
SDA
SCL
Figure
CK
page 125
/ 2. This is also the maximum data transmit and
14-6. The SDA line is delayed (in the range of 50
23) must also be taken into consideration.
D Q
CLR
for further details.
D Q
CLR
ATtiny24/44/84
USISIF
CLOCK
HOLD
123