ata5773 ATMEL Corporation, ata5773 Datasheet - Page 125

• Manufacturer Part Number: ata5773
• Description: Microcontroller With Uhf Ask/fsk Transmitter
• Manufacturer: ATMEL Corporation

11.6.1
11.7
11.7.1
11.7.2
8006G–AVR–01/08
Modes of Operation
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The design of the Output Compare pin logic allows initialization of the OC0x state before the out-
put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation, see
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the
OC0x Register is to be performed on the next Compare Match. For compare output actions in
the non-PWM modes refer to
page
A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the 0x
strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output
mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare
Match (See
For detailed timing information refer to
11-10 on page 78
77.
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the Compare Match output frequency. It
also simplifies the operation of counting external events.
80, and for phase correct PWM refer to
“Modes of Operation” on page
“Register Description” on page 79
and
Figure 11-11 on page 79
Table 11-2 on page
Figure 11-8 on page
73).
Table 11-4 on page
79. For fast PWM mode, refer to
in
“Timer/Counter Timing Diagrams” on page
78,
Figure 11-9 on page
80.
ATtiny24/44/84
Table 11-3 on
78,
Figure
73