ata5773 ATMEL Corporation, ata5773 Datasheet - Page 157

• Manufacturer Part Number: ata5773
• Description: Microcontroller With Uhf Ask/fsk Transmitter
• Manufacturer: ATMEL Corporation

12.10 Timer/Counter Timing Diagrams
8006G–AVR–01/08
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COM1x1:0 to three (See
page
port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)
the OC1x Register at the compare match between OCR1x and TCNT1 when the counter incre-
ments, and clearing (or setting) the OC1x Register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
ting of OCF1x.
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
I/O
Tn
108). The actual OC1x value will only be visible on the port pin if the data direction for the
/1)
OCRnx - 1
f
OCnxPFCPWM
Figure 12-10 on page 105
OCRnx
OCRnx Value
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
shows a timing diagram for the set-
OCRnx + 1
ATtiny24/44/84
T1
) is therefore shown as a
OCRnx + 2
Table 12-4 on
105