lmp8100 National Semiconductor Corporation, lmp8100 Datasheet - Page 24

• Manufacturer Part Number: lmp8100
• Description: Programmable Gain Amplifier
• Manufacturer: National Semiconductor Corporation

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SERIAL CONTROL INTERFACE OPERATION
The LMP8100 gain, bandwidth compensation, power down,
and input zeroing are controlled by data stored in a program-
ming register. Data to be written into the control register is first
loaded into the LMP8100 via the serial interface. The serial
interface employs an 8-bit shift register. Data is loaded
through the serial data input, SDI. Data passing through the
shift register is output through the serial data output, SDO.
FIGURE 12. Non-Inverting Input Zeroing Function
FIGURE 13. Serial Control Interface Timing
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The serial clock, SCK controls the serial loading process. All
eight data bits are required to correctly program the amplifier.
The falling edge of CS enables the shift register to receive
data. The SCK signal must be high during the falling and rising
edge of CS. Each data bit is clocked into the shift register on
the rising edge of SCK. Data is transferred from the shift reg-
ister to the holding register on the rising edge of CS. Operation
is shown in the timing diagram,Figure 13.
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