lmp8100 National Semiconductor Corporation, lmp8100 Datasheet - Page 22

• Manufacturer Part Number: lmp8100
• Description: Programmable Gain Amplifier
• Manufacturer: National Semiconductor Corporation

www.national.com
AMPLIFIER GAIN SETTING AND BANDWIDTH
COMPENSATION CONTROL
The gain of the LMP8100 is set to one of 16 levels under pro-
gram control by setting the appropriate bits G[3:0] of the
control register with a number from 00h to 15h. This sets the
gain to a level from 1 V/V to 16 V/V respectively.
The gain-bandwidth compensation is also selectable to one
of four levels under program control. The amount of compen-
sation can be decreased to maximize the available bandwidth
as the gain of the amplifier is increased. The compensation
level is selected by setting bits C[1:0] of the control register
with a number from 00b to 11b with 00b being maximum com-
pensation and 11b being minimum compensation. Table 4
shows the bandwidths achieved at several gain and compen-
sation settings. It will be noted that for gains between X1 and
X5, the recommended compensation setting is 00b. For gain
settings between X6 and X10, compensation settings may be
00b and 01b. Gain settings between X11 and X15 may use
the three bandwidth compensation settings between 00b and
10b. At a gain of X16, all bandwidth compensation ranges
may be used. Note that, for lower gains, it is possible to under-
compensate the amplifier into instability.
Zero
X
1
C1
0
0
1
1
TABLE 3. Amplifier Gain Compensation Codes
PD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
TABLE 2. Input Zero, Power-Down
C0
0
1
0
1
G3
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
and Gain Setting Codes
Compensation
G2
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Level
0
1
2
3
G1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
G0
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Compensation
Compensation
Condition
Non-Inverting
Maximum
Minimum
Power Down
Zero Input
Gain
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
22
NON-INVERTING AMPLIFIER OPERATION
The principal application of the LMP8100 is as a non-inverting
amplifier as shown in the simplified schematic, Figure 9. The
amplifier supply voltage (V
mum. The V
for single supply operation. V
voltage when required by the application. The digital supply
voltage for the serial interface is applied between the V
ply pin and DGND.
V/V
11
11
11
16
16
16
16
1
2
6
6
Gain
TABLE 4. Amplifier Gain and Compensation
FIGURE 9. Basic Non-Inverting Amplifier
6.02
15.6
15.6
20.8
20.8
20.8
24.1
24.1
24.1
24.1
dB
0
–
supply pin is connected to the system ground
Compensation Bits
vs. Bandwidth
C1
0
0
0
0
0
0
1
0
0
1
1
+
to V
−
can be returned to a negative
−
) is specified as 5.5V maxi-
C0
0
0
0
1
0
1
0
0
1
0
1
3 dB Bandwidth
(MHz)
33.0
15.5
4.2
8.3
2.0
3.9
6.6
1.3
2.3
3.8
9.5
+
sup-
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