lmp8100 National Semiconductor Corporation, lmp8100 Datasheet

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lmp8100

Manufacturer Part Number
lmp8100
Description
Programmable Gain Amplifier
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2007 National Semiconductor Corporation
LMP8100
Programmable Gain Amplifier
General Description
The LMP8100 programmable gain amplifier features an ad-
justable gain from 1 to 16 V/V in 1 V/V increments. At the core
of the LMP8100 is a precision, 33 MHz, CMOS input, rail-to-
rail input/output operational amplifier with a typical open-loop
gain of 110 dB. Amplifier closed-loop gain is set by an array
of precision thin-film resistors. Amplifier control modes are
programmed via a serial port that allows devices to be cas-
caded so that an array of LMP8100 amplifiers can be pro-
grammed by a single serial data stream. The control mode
registers are double buffered to insure glitch-free transitions
between programmed settings. The LMP8100 is part of the
LMP
applications.
The amplifier features several programmable controls includ-
ing: gain; a power-conserving shutdown mode which can
reduce current consumption to only 20 μA; an input zeroing
switch which allows the output offset voltage to be measured
to facilitate system calibration; and four levels of internal fre-
quency compensation which can be set to maximize band-
width at the different gain settings.
The LMP8100 comes in a 14-Pin SOIC package.
Simplified Block Diagram
LMP
®
is a registered trademark of National Semiconductor Corporation.
®
precision amplifier family and is ideal for a variety of
201476
Features
Typical Values, T
Applications
Gain error (over temperature range)
— LMP8100A
— LMP8100
Gain range
Programmable frequency compensation
Input zero calibration switch
Input offset voltage (max, LMP8100A)
Input bias current
Input noise voltage
Unity gain bandwidth
Slew rate
Output current
Supply voltage range
Supply current
Rail-to-Rail output swing
Industrial instrumentation
Data acquisition systems
Test equipment
Scaling amplifier
Gain control
Sensor interface
A
= 25°C
20147607
1 to 16 V/V in 1 V/V steps
V
+
−50 mV to V
www.national.com
2.7V to 5.5V
12 nV/
July 2007
33 MHz
+50 mV
0.075%
12 V/μs
250 μV
5.3 mA
0.1 pA
20 mA
0.03%
Hz

Related parts for lmp8100

lmp8100 Summary of contents

Page 1

... Amplifier closed-loop gain is set by an array of precision thin-film resistors. Amplifier control modes are programmed via a serial port that allows devices to be cas- caded so that an array of LMP8100 amplifiers can be pro- grammed by a single serial data stream. The control mode registers are double buffered to insure glitch-free transitions between programmed settings ...

Page 2

Block Diagram www.national.com 2 20147602 ...

Page 3

... Unless otherwise specified, all limits are guaranteed for T kΩ /2; Gain = 1 V/V. Boldface limits apply at the temperature extremes. Symbol Parameter Gain Error LMP8100A Gain Error LMP8100 LMP8100 Gain Error (Gain = 1 V/V) Extended +IN Range TCGE Gain Drift LMP8100A LMP8100 V Input Offset Voltage LMP8100A OS ...

Page 4

... Unless otherwise specified, all limits are guaranteed for kΩ /2; Gain = 1 V/V. Boldface limits apply at the temperature extremes. L Symbol Parameter Gain Error LMP8100A Gain Error LMP8100 LMP8100 Gain Error (Gain = 1 V/V) Extended +IN Range TCGE Gain Drift LMP8100A LMP8100 V Input Offset Voltage LMP8100A OS LMP8100 TCV ...

Page 5

Electrical Characteristics (Serial Interface) Unless otherwise specified, all limits guaranteed for T Symbol Parameter V Logic Low Threshold IL V Logic High Threshold IH I Output Source Current, SDO SDO Output Sink Current, SDO I Output Tri-state Leakage Current, OZ ...

Page 6

... Connection Diagram Ordering Information Package Part Number LMP8100AMA LMP8100AMAX 14-Pin SOIC LMP8100MA LMP8100MAX www.national.com 14-Pin SOIC 20147601 Top View Package Marking Transport Media 55 Units/Rail LMP8100AMA 2.5k units Tape and Reel 55 Units/Rail LMP8100MA 2.5k units Tape and Reel 6 NSC Drawing M14A ...

Page 7

Timing Diagram Test Circuit Timing Diagram 20147653 7 20147603 www.national.com ...

Page 8

Test Circuit Diagram www.national.com Test Circuit 8 20147609 ...

Page 9

Typical Performance Characteristics Offset Voltage Distribution TCV Distribution Offset Voltage Distribution 20147685 TCV 20147683 20147666 9 20147686 Distribution OS 20147684 V vs 20147667 www.national.com ...

Page 10

www.national.com S 20147665 20147662 S 20147660 20147664 I vs 20147663 I vs 20147661 ...

Page 11

DC Gain Error Gain Error Small Signal Gain Error vs. +IN DC Level DC Gain Error 20147689 DC Gain Error 20147690 Small Signal Gain Error vs. +IN ...

Page 12

PSRR vs. Frequency I vs. V (Source) OUT OUT I vs. V (Source) OUT OUT www.national.com PSRR vs. Frequency 20147610 I OUT 20147669 I OUT 20147671 12 20147611 vs. V (Sink) OUT 20147668 vs. V (Sink) OUT 20147670 ...

Page 13

Small Signal Step Response 20147635 Small Signal Step Response 20147637 Small Signal Step Response 20147639 Small Signal Step Response Small Signal Step Response Small Signal Step Response 13 20147636 20147638 20147640 www.national.com ...

Page 14

Small Signal Step Response Large Signal Step Response Large Signal Step Response www.national.com Small Signal Step Response 20147641 Large Signal Step Response 20147643 Large Signal Step Response 20147645 14 20147642 20147644 20147646 ...

Page 15

Large Signal Step Response 20147647 Large Signal Step Response 20147649 THD+N vs. Frequency 20147675 Large Signal Step Response Large Signal Step Response THD+N vs. Frequency 15 20147648 20147650 20147674 www.national.com ...

Page 16

THD+N vs. V Bandwidth vs. Capacitive Load Peaking vs. Capacitive Load www.national.com OUT 20147673 20147617 20147621 16 THD+N vs. V OUT 20147672 Bandwidth vs. Capacitive Load 20147618 Peaking vs. Capacitive Load 20147622 ...

Page 17

Peaking vs. Capacitive Load 20147623 Gain vs. Frequency 20147629 Gain vs. Frequency 20147627 Gain vs. Frequency Gain vs. Frequency AC Gain Error vs. Frequency 17 20147630 20147628 20147656 www.national.com ...

Page 18

AC Gain Error vs. Frequency AC Gain Error vs. Frequency Noise vs. Frequency www.national.com AC Gain Error vs. Frequency 20147655 AC Gain Error vs. Frequency 20147658 0 Noise 20147654 18 20147657 20147659 201476a2 ...

Page 19

Closed Loop Output Impedance vs. Frequency SDO V vs. I Input Impedance 20147631 20147634 19 201476a1 SDO V vs. I 20147652 www.national.com ...

Page 20

... This is due to the very low off- set voltage specification and very precise gain specification of the LMP8100. The LMP8100 has an option to zero out the offset voltage. When the zero bit of the register is set high, +IN is connected to GRT. Output offset voltage can be mea- sured and adjusted out of the signal path. See the “ ...

Page 21

... FIGURE 7. THBT Gain Drift FIGURE 8. THBT Gain Drift POWER-ON RESET The LMP8100 has a power-up reset feature that sets all the register bits to 0 when the part is powered up. To implement this feature the CS and SCK pins must be held at or above V when the LMP8100 is powered-up ...

Page 22

... AMPLIFIER GAIN SETTING AND BANDWIDTH COMPENSATION CONTROL The gain of the LMP8100 is set to one of 16 levels under pro- gram control by setting the appropriate bits G[3:0] of the control register with a number from 00h to 15h. This sets the gain to a level from 1 V V/V respectively. ...

Page 23

... ADC under microprocessor control. Output offset is measured under program control by setting the ZERO bit in the programming register. In this mode, +IN is disconnected from the input pin and internally connected to 20147679 the GRT input. Figure 12 shows the LMP8100 in the input zeroing mode. 23 20147676 for offset correction OUT www ...

Page 24

... Data to be written into the control register is first loaded into the LMP8100 via the serial interface. The serial interface employs an 8-bit shift register. Data is loaded through the serial data input, SDI. Data passing through the shift register is output through the serial data output, SDO ...

Page 25

... Byte one sent 10001010 Byte two sent 10001010 Byte three sent 10001010 If LMP8100 #1 needs a gain of 11 with a compensation level of 10 (10001010), LMP8100 #2 needs a gain of 6 with a compensation of 00 (00000101), and LMP8100 #3 needs a gain of 2 with a compensation of 00 (00000001). Register of LMP8100 #1 Power on 00000000 ...

Page 26

... FIGURE 15. Daisy Chain Configuration SCALING AMPLIFIER The LMP8100 is ideally suited for use as an amplifier between a sensor that has a wide output range and an ADC. As the signal from the sensor changes the gain of the LMP8100 can be changed so that the entire input range of the ADC is being used at all times. Figure 16 shows a data acquisition system using the LMP8100 and the ADC121S101. The 100Ω ...

Page 27

... LMP7711 can be set to supply a full range signal to the ADC input with the gain of the LMP8100 set to one. As the magnetic field decreases, the gain of the LMP8100 can be increased, so that the signal supplied to the ADC uses a maximum amount of the ADC input range ...

Page 28

Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 14-Pin SOIC NS Package Number M14A 28 ...

Page 29

Notes 29 www.national.com ...

Page 30

... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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