lmp8100 National Semiconductor Corporation, lmp8100 Datasheet - Page 23

• Manufacturer Part Number: lmp8100
• Description: Programmable Gain Amplifier
• Manufacturer: National Semiconductor Corporation

GRT PINS
The GRT pins must have a low impedance connection to ei-
ther ground or a reference voltage. Any parasitical impedance
on these pins will affect the gain accuracy of the LMP8100.
Figure 10 shows a simplified schematic of the LMP8100
showing the internal gain resistors and an external parasitical
resistance RP. The gain of the LMP8100 is determined by
R
The gain of the amplifier is given by the equation
Any resistance between the GRT pins and either ground or a
reference voltage will change the gain to
The connection between the GRT pins and ground or a ref-
erence voltage should be as short as possible using wide
F
and R
FIGURE 10. LMP8100 with External Parasitical
G
, the values of which are set by the internal register.
Resistance
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traces to minimize the parasitical resistance. Figure 11 shows
two suggested methods of connecting the GRT pins to a
ground plane on the same layer or to a ground plane on a
different layer of the PCB.
The GRT pin can be connected to a reference voltage source
to provide an offset adjustment to the gain function. Any DC
resistance that may be present between the voltage source
and the GRT pin must be kept to an absolute minimum to
avoid introducing gain errors into the circuit.
INPUT ZEROING
Measurements made with the LMP8100 in the signal path
may be adjusted for the output offset voltage of the amplifier.
For example: The measurement of V
might be made using an ADC under microprocessor control.
Output offset is measured under program control by setting
the ZERO bit in the programming register. In this mode, +IN
is disconnected from the input pin and internally connected to
the GRT input. Figure 12 shows the LMP8100 in the input
zeroing mode.
FIGURE 11. GRT Connection Methods
OUT
for offset correction
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