m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 66

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

A-D CONVERTER
[A-D Conversion Register 1, 2 (AD1, AD2)]
0035
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode se-
lection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
not only 10-bit reading but also only high-order 8-bit reading of
conversion result can be performed by selecting the reading pro-
cedure of the A-D conversion registers 1, 2 after A-D conversion is
completed (in Figure 58).
As for 10-bit A-D mode, the 8-bit reading inclined to MSB is per-
formed when reading the A-D converter register 1 after A-D
conversion is started; and when the A-D converter register 1 is
read after reading the A-D converter register 2, the 8-bit reading
inclined to LSB is performed.
[AD/DA Control Register (ADCON)] 0034
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
V
in the 10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
V
input voltage.
• 10-bit A-D mode (10-bit reading)
• 10-bit A-D mode (8-bit reading)
• 8-bit A-D mode
66
V
V
V
REF
ref
ref
ref
ref
in each mode, dividing the V
=
=
=
=0
and AV
16
V
1024
V
V
256
256
REF
REF
REF
, 0038
SS
into 1024, and that outputs the comparison voltage
n (n = 0–1023)
n (n = 0–255)
(n–0.5) (n = 1–255)
16
(n = 0)
REF
voltage (see below), with the
16
Channel Selector
The channel selector selects one of ports P6
P0
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
Fig. 57 Structure of AD/DA control register
Fig. 58 Structure of 10-bit A-D mode reading
7
/AN
b 7
N o t e : Bi t s 2 t o 6 o f a d d r e s s 0 0 3 8
1 0 - b i t r e a d i n g
8 - b i t r e a d i n g
15
( R e a d a d d r e s s 0 0 3 8
A - D c o n v e r s i o n r e g i s t e r 2
( A D 2 : a d d r e s s 0 0 3 8
A - D c o n v e r s i o n r e g i s t e r 1
( A D 1 : a d d r e s s 0 0 3 5
( R e a d o n l y a d d r e s s 0 0 3 5
A - D c o n v e r s i o n r e g i s t e r 1
( A D 1 : a d d r e s s 0 0 3 5
to P0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
a t r e a d i n g .
IN
) to 500 kHz or more during an A-D conversion.
0
/AN
8
, and inputs the voltage to the comparator.
MITSUBISHI MICROCOMPUTERS
1 6
1 6
1 6
b 0
1 6
)
)
)
b e f o r e 0 0 3 5
3803/3804 Group
1 6
AD/DA control register
(ADCON : address 0034
A D c o n v e r s i o n c o m p l e t i o n b i t
A n a l o g i n p u t p i n s e l e c t i o n b i t 2
D A
D A
A n a l o g i n p u t p i n s e l e c t i o n b i t s 1
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
)
1 6
1
2
b 2 b 1 b 0
0 0 0 : P 6
0 0 1 : P 6
0 1 0 : P 6
0 1 1 : P 6
1 0 0 : P 6
1 0 1 : P 6
1 1 0 : P 6
1 1 1 : P 6
0 : C o n v e r s i o n i n p r o g r e s s
1 : C o n v e r s i o n c o m p l e t e d
0 : A N
1 : A N
0 : D A
1 : D A
0 : D A
1 : D A
o u t p u t e n a b l e b i t
o u t p u t e n a b l e b i t
b 7
b 7
b 7
0
b 7 b 6 b 5 b 4 b 3 b 2 b 1 b0
b 9 b 8 b 7 b 6 b 5 b 4 b 3 b2
b e c o m e “ 0 ”
0
8
1
1
2
2
1 6
t o A N
t o A N
o u t p u t d i s a b l e d
o u t p u t e n a b l e d
o u t p u t d i s a b l e d
o u t p u t e n a b l e d
)
0
1
2
3
4
5
6
7
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
7
7
1 5
/AN
s i d e
0
1
2
3
4
5
6
7
s i d e
o r P 0
o r P 0
o r P 0
o r P 0
o r P 0
o r P 0
o r P 0
o r P 0
7
16
to P6
)
0
1
2
3
4
5
6
7
b 9
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
b0
b 8
b0
b0
0
8
9
1 0
1 1
1 2
1 3
1 4
1 5
/AN
0
or