m38039mf-xxxsp Mitsumi Electronics, Corp., m38039mf-xxxsp Datasheet - Page 37

• Manufacturer Part Number: m38039mf-xxxsp
• Description: Single-chip 8-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

TIMERS
The 3803/3804 group has four 8-bit timers: timer 1, timer 2, timer
X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “00
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt re-
quest bit corresponding to that timer is set to “1”.
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B
(middle-speed mode), X
(low-speed mode), X
The prescaler 12 counts the output of the timer divider. The count
source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512,
1/1024 of f(X
Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and pe-
riodically set the interrupt request bit.
The prescaler X and prescaler Y count the output of the timer
divider or f(X
count source selection register (address 000E
Z count source selection register (address 000F
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(X
or f(X
Timer divider
Prescaler 12
Prescaler X and prescaler Y
8-bit Timers
16
CIN
). When these bits are “00” (high-speed mode) or “01”
); and f(X
IN
CIN
) or f(X
). The count source is selected by the timer 12, X
CIN
CIN
).
CIN
is selected.
).
IN
is selected. When these bits are“10”
16
) and the timer Y,
16
) among 1/2,
16
”, an
IN
)
Timer X and Timer Y
The timer X and timer Y can each select one of four operating
modes by setting the timer XY mode register (address 0023
(1) Timer mode
This mode can be selected by setting “00” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 0023
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 0023
When the timer reaches “00
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
(2) Pulse output mode
This mode can be selected by setting “01” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 0023
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR
(bit 2) and the CNTR
mode register (address 0023
level. When it is “1”, the output starts with “L” level.
When the value of the CNTR
changed during pulse output, the output level of the CNTR
CNTR
Set the double-function port of CNTR
P5
Precautions
Mode selection
Explanation of operation
Mode selection
Explanation of operation
5
to output in this mode.
1
pin is inverted.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
0
/CNTR
1
1
pin. When the CNTR
MITSUBISHI MICROCOMPUTERS
active edge switch bit (bit 6) of the timer XY
16
16
3803/3804 Group
0
”, an underflow occurs at the next
/CNTR
) is “0”, the output starts with “H”
16
0
1
/CNTR
).
active edge switch bit is
0
active edge switch bit
1
pin and port P5
16
16
).
).
16
).
37
0
4
/
/