m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 70

• Manufacturer Part Number: m30262f8gp
• Description: Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

Watchdog Timer
64
Watchdog Timer
With X
Watchdog timer period =
With X
Watchdog timer period =
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer
interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. When the
watchdog timer interrupt is selected, write to the watchdog timer start register after the watchdog timer
interrupt occurs (initialize watchdog timer). Watchdog timer interrupt is selected when bit 2 (PM12) of the
processor mode register 1 (address 0005
than “1” can be written in PM12. Once when reset is selected (PM12=“1”), watchdog timer interrupt cannot
be selected by software.
When X
prescaler division ratio (by 16 or by 128). When X
division by 2 regardless of bit 7 of the watchdog timer control register (address 000F
dog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an
error due to the prescaler.
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer
is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started
by writing to the watchdog timer start register (address 000E
the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes
or state are released.
Also PM12 is initialized only when reset. The watchdog timer interrupt is selected after reset is cancelled.
Figure 1.10.1 shows the block diagram of the watchdog timer. Figure 1.10.2 shows the watchdog timer-
related registers.
IN
CIN
IN
chosen for BCLK
chosen for BCLK
is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
prescaler dividing ratio (2) X watchdog timer count (32768)
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
Renesas Technology Corp.
16
) is “0” and reset is selected when PM12 is “1”. No value other
CIN
is selected as the BCLK, the prescaler is set for
BCLK
16
). In stop mode, wait mode and hold state,
BCLK
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
). Thus the watch-
M16C/26 Group
16
16
) selects the
) and when