m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 144

• Manufacturer Part Number: m30262f8gp
• Description: Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

Clock Asynchronous Serial I/O (UART) Mode
138
Figure 1.15.24. Typical transmit/receive timing in UART mode (used for SIM interface)
Note : Equal in waveform because TxD
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxD
RxD
Signal conductor level
(Note)
Transmit register
empty flag (TXEPT)
Transmit interrupt
request bit (IR)
Transfer clock
Receive enable
bit (RE)
RxD
TxD
Signal conductor level
(Note)
Receive complete
flag (RI)
Receive interrupt
request bit (IR)
Note : Equal in waveform because TxD
2
2
2
2
Preliminary Specifications Rev. 0.9
Shown in ( ) are bit symbols.
Specifications in this manual are tentative and subject to change.
The above timing applies to the following settings :
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
1
0
1
0
1
0
1
0
1
0
* Parity is enabled.
* One stop bit.
* Transmit interrupt cause select bit = 0 .
* Parity is enabled.
* One stop bit.
* Transmit interrupt cause select bit = 1 .
1
0
1
0
ST
ST
Start
Start
ST
ST
bit
bit
D
D
D
D
0
0
0
0
2
Data is set in UART2 transmit buffer register
D
D
D
D
2
and RxD
1
1
1
1
Tc
Tc
and RxD
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
Renesas Technology Corp.
2
D
D
D
D
2
are connected.
4
4
4
4
are connected.
D
D
D
D
5
5
5
5
D
D
Transferred from UART2 transmit buffer register to UART2 transmit register
D
D
6
6
6
6
D
D
D
D
Parity
Parity
7
7
7
7
bit
bit
Tc = 16 (n + 1) / fi
Tc = 16 (n + 1) / fi
P
P
P
P
Cleared to 0 when interrupt request is accepted, or cleared by software
SP
Cleared to 0 when interrupt request is accepted, or cleared by software
SP
SP
SP
fi : frequency of BRG2 count source (f
n : value set to BRG2
fi : frequency of BRG2 count source (f
n : value set to BRG2
Stop
Stop
bit
bit
Read to receive buffer
ST
ST
ST
The level is detected by the
interrupt routine.
ST
An L level returns from TxD
the occurrence of a parity error.
An L level returns from TxD
the occurrence of a parity error.
D
D
D
D
0
0
0
0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
1SIO
1SIO
D
D
5
5
5
5
2
D
D
due to
2
D
D
, f
, f
6
6
due to
6
6
2SIO
2SIO
D
D
D
D
7
7
7
7
, f
, f
P
P
P
P
8SIO
8SIO
M16C/26 Group
Read to receive buffer
SP
SP
, f
, f
SP
SP
32SIO
32SIO
The level is
detected by the
interrupt routine.
)
)