m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 32
m30262f8gp
Manufacturer Part Number
m30262f8gp
Description
Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M30262F8GP.pdf
(239 pages)
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Processor Mode
26
Software Reset
Processor mode register 2 (Note 1)
Figure 1.7.2. Processor mode register 2
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a
microcomputer. A software reset has the same effect as a hardware reset except the contents of internal
RAM are preserved after a software reset.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A
b7
b6
b5
Preliminary Specifications Rev. 0.9
b4
0
Specifications in this manual are tentative and subject to change.
b3
0 0 0
b2
b1
16
b0
0
) to “1”.
Note 1: Set bit 1 of the protect register (address 000A
Note 2: When the system clock is 16Mhz and more, must set to 2 waits.
Note 3: This bit cannot be changed from "1" to "0" in software.
Note 4: Setting PM21 to "1" results in the following:
Note 5: Setting PM22 to "1" results in the following:
Note 6: For NMI function, this bit must be set to "1" in first instruction after reset.
Note 7: When this bit is set to "1", the P8
Nothing is assigned.
Writes must set each bit to "0". Read values are indeterminate.
Bit symbol
PM20
PM21
Reserved bit
PM24
PM22
Symbol
PM2
to this register.
• BCLK is not halted by WAIT instruction.
• Writing to the following bits has no effect:
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the
• Writing to CM10 disabled (stop mode is not entered).
• Watchdog timer does not stop when in wait mode or hold state.
watchdog timer count source.
CM02, of register CM0
CM05, of register CM0 (main clock is not halted)
CM07, of register CM0 (CPU clock source does not change)
CM10, of register CM1 (stop mode is not entered)
CM20, of register CM2 (oscillation stop, re-oscillation detection function settings
do not change)
Renesas Technology Corp.
Specifying wait when
accessing SFR registers
(Note 2)
System clock protective bit
(Notes 3,4)
P8
(Notes 3,6,7)
WDT count source
protective bit (Notes 3,5)
5
/NMI configuration bit
Bit name
Address
001E
16
5
direction register must be "0".
When reset
XXX00000
0 : 2 waits
1 : 1 wait
0: P8
1: NMI function
0 : Clock is protected by PRCR
1 : Clock modification disabled
0 : CPU clock is used for the
1 : Ring oscillator clock is used
Must always be set to "0"
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
watchdog timer count source
for the watchdog timer count
source
register
5
function (NMI disable)
16
2
) to "1" before writing new values
Function
(s
oftware) reset to the
M16C/26 Group
R
W
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