scf5249 Freescale Semiconductor, Inc, scf5249 Datasheet - Page 26

• Manufacturer Part Number: scf5249
• Description: Scf5249 Integrated Coldfire
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
8.19.5 Processor Status
The processor status pins, PST0_GPIO59, PST1_GPIO60, PST2_GPIO61, and PST3_GPIO62, indicate
the SCF5249 processor status. During debug mode, the timing is synchronous with the processor clock
(PSTCLK) and the status is not related to the current bus transfer. .
8.20 BDM/JTAG Signals
The SCF5249 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed
with background debug pins.
8.20.1 Test Clock
TCK is the dedicated JTAG test logic clock that is independent of the SCF5249 processor clock. Various
JTAG operations occur on the rising or falling edge of TCK. The internal JTAG controller logic is designed
such that holding TCK high or low for an indefinite period of time will not cause the JTAG test logic to
lose state information. If TCK will not be used, it should be tied to ground.
26
(HEX)
$A
$B
$C
$D
$E
$F
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
Notes:
4.
5.
PST[3:0]
Rev. B enhancement.
These encodings are asserted for multiple cycles.
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
(BINARY)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 14. Processor Status Signal Encodings
Continue execution
Begin execution of an instruction
Reserved
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch or Synch_PC
Reserved
Begin execution of RTE instruction
Begin 1-byte data transfer on DDATA
Begin 2-byte data transfer on DDATA
Begin 3-byte data transfer on DDATA
Begin 4-byte data transfer on DDATA
Exception processing
Emulator mode entry exception processing
Processor is stopped, waiting for interrupt
Processor is halted
Entry into user-mode
2
2
Definition
2
2
1
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