scf5249 Freescale Semiconductor, Inc, scf5249 Datasheet - Page 10

• Manufacturer Part Number: scf5249
• Description: Scf5249 Integrated Coldfire
• Manufacturer: Freescale Semiconductor, Inc

SCF5249 Functional Overview
The CD-ROM decoder performs following functions in hardware:
The CD-ROM encoder performs following functions in hardware:
5.13 Dual UART Module
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats
can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte
receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function from a programmable prescaler. You can select full
duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs
can interrupt the CPU on various normal or error-condition events.
5.14 Queued Serial Peripheral Interface QSPI
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to
16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
37 Mbits/second are possible at a CPU clock of 140 MHz. The QSPI supports master mode operation only.
5.15 Timer Module
The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer
for use in any of three modes:
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock
(CPU clock / 2), the programmable timer-output pins either generate an active-low pulse or toggle the
outputs.
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1. Timer Capture. This mode captures the timer value with an external event.
2. Output Capture. This mode triggers an external signal or interrupts the CPU when the timer
3. Event Counter. This mode counts external events.
Sector sync recognition
Descrambling of sectors
Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors
Third-layer error correction is not performed
Sector sync recognition
Scrambling of sectors
Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
Third-layer error encoding needs to be done in software. This can use approximately 5-10 Mhz of
performance for single-speed.
reaches a set value
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor