cop8cde9 National Semiconductor Corporation, cop8cde9 Datasheet - Page 61

• Manufacturer Part Number: cop8cde9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, 10-bit A/d And Brownout Reset
• Manufacturer: National Semiconductor Corporation

13.0 Memory Map
Note: Reading memory locations 0070H–007FH (Segment 0) will return all
14.0 Instruction Set
14.1 INTRODUCTION
This section defines the instruction set of the COP8 Family
members. It contains information about the instruction set
features, addressing modes and types.
14.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the following
features:
• Mostly single-byte opcode instructions minimize program
• One instruction cycle for the majority of single-byte in-
• Many single-byte, multiple function instructions such as
xxD7 to xxDB
xxDC
xxDD
xxDE
xxDF
xxE0
xxE1
xxE2
xxE3 to xxE5
xxE6
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
xxEE
xxEF
xxF0 to FB
xxFC
xxFD
xxFE
xxFF
0100 to 017F
S/ADD REG
size.
structions to minimize program execution time.
DRSZ.
Address
ones. Reading unused memory locations 0080H–0093H (Segment 0)
will return undefined data. Reading memory locations from other Seg-
ments (i.e., Segment 8, Segment 9, … etc.) will return undefined data.
Reserved
Port H Data Register
Port H Configuration Register
Port H Input Pins (Read Only)
Reserved for Port H
Reserved
Flash Memory Write Timing Register
(PGMTIM)
ISP Key Register (ISPKEY)
Reserved
Timer T1 Autoload Register T1RB Lower
Byte
Timer T1 Autoload Register T1RB Upper
Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower
Byte
Timer T1 Autoload Register T1RA Upper
Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register
On-Chip 128 RAM Bytes
(Continued)
Contents
61
14.3 ADDRESSING MODES
The instruction set offers a variety of methods for specifying
memory addresses. Each method is called an addressing
mode. These modes are classified into two categories: op-
erand addressing modes and transfer-of-control addressing
modes. Operand addressing modes are the various meth-
ods of specifying an address for accessing (reading or writ-
ing) data. Transfer-of-control addressing modes are used in
conjunction with jump instructions to control the execution
sequence of the software program.
14.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory loca-
tion is to be affected by that instruction. Several different
operand addressing modes are available, allowing memory
locations to be specified in a variety of ways. An instruction
can specify an address directly by supplying the specific
address, or indirectly by specifying a register pointer. The
contents of the register (or in some cases, two registers)
point to the desired memory location. In the immediate
mode, the data byte to be used is contained in the instruction
itself.
Each addressing mode has its own advantages and disad-
vantages with respect to flexibility, execution speed, and
program compactness. Not all modes are available with all
instructions. The Load (LD) instruction offers the largest
number of addressing modes.
The available addressing modes are:
The addressing modes are described below. Each descrip-
tion includes an example of an assembly language instruc-
tion using the described addressing mode.
Direct. The memory address is specified directly as a byte in
the instruction. In assembly language, the direct address is
written as a numerical value (or a label that has been defined
elsewhere in the program as a numerical value).
Example: Load Accumulator Memory Direct
• Three memory mapped pointers: two for register indirect
• Sixteen memory mapped registers that allow an opti-
• Ability to set, reset, and test any individual bit in data
• Register-Indirect LOAD and EXCHANGE instructions
• Unique instructions to optimize program size and
• Direct
• Register B or X Indirect
• Register B or X Indirect with Post-Incrementing/
• Immediate
• Immediate Short
• Indirect from Program Memory
addressing, and one for the software stack.
mized implementation of certain instructions.
memory address space, including the memory-mapped
I/O ports and registers.
with optional automatic post-incrementing or decrement-
ing of the register pointer. This allows for greater effi-
ciency (both in cycle time and program code) in loading,
walking across and processing fields in data memory.
throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
Decrementing
LD A,05
www.national.com