cop8cde9 National Semiconductor Corporation, cop8cde9 Datasheet - Page 34

• Manufacturer Part Number: cop8cde9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, 10-bit A/d And Brownout Reset
• Manufacturer: National Semiconductor Corporation

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7.0 Power Saving Features
7.3.2 High Speed Idle Mode
In the IDLE mode, program execution stops and power
consumption is reduced to a very low level as with the HALT
mode. However, the high speed oscillator, IDLE Timer (Timer
T0), and Clock Monitor continue to operate, allowing real
time to be maintained. The device remains idle for a selected
amount of time up to 65,536 instruction cycles, or 32.768
milliseconds with a 2 MHz instruction clock frequency, and
then automatically exits the IDLE mode and returns to nor-
mal program execution.
The device is placed in the IDLE mode under software
control by setting the IDLE bit (bit 6 of the Port G data
register).
The IDLE Timer window is selectable from one of five values,
4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this
value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to
keep track of elapsed time in the IDLE state. The IDLE Timer
runs continuously at the instruction clock rate, whether or not
the device is in the IDLE mode. Each time the bit of the timer
associated with the selected window toggles, the T0PND bit
is set, an interrupt is generated (if enabled), and the device
exits the IDLE mode if in that mode. If the IDLE Timer
interrupt is enabled, the interrupt is serviced before execu-
tion of the main program resumes. (However, the instruction
which was started as the part entered the IDLE mode is
completed before the interrupt is serviced. This instruction
should be a NOP which should follow the enter IDLE instruc-
tion.) The user must reset the IDLE Timer pending flag
(T0PND) before entering the IDLE mode.
As with the HALT mode, this device can also be returned to
normal operation with a reset, or with a Multi-Input Wake-up
input. Upon reset the ITMR register is cleared and the ITMR
register selects the 4,096 instruction cycle tap of the Idle
Timer.
The IDLE Timer cannot be started or stopped under software
control, and it is not memory mapped, so it cannot be read or
written by the software. Its state upon Reset is unknown.
Therefore, if the device is put into the IDLE mode at an
arbitrary time, it will stay in the IDLE mode for somewhere
between 1 and the selected number of instruction cycles.
FIGURE 20. Wake-up from HALT
(Continued)
34
In order to precisely time the duration of the IDLE state, entry
into the IDLE mode must be synchronized to the state of the
IDLE Timer. The best way to do this is to use the IDLE Timer
interrupt, which occurs on every underflow of the bit of the
IDLE Timer which is associated with the selected window.
Another method is to poll the state of the IDLE Timer pending
bit T0PND, which is set on the same occurrence. The Idle
Timer interrupt is enabled by setting bit T0EN in the ICNTRL
register.
Any time the IDLE Timer window length is changed there is
the possibility of generating a spurious IDLE Timer interrupt
by setting the T0PND bit. The user is advised to disable
IDLE Timer interrupts prior to changing the value of the
ITSEL bits of the ITMR Register and then clear the TOPND
bit before attempting to synchronize operation to the IDLE
Timer.
Note: As with the HALT mode, it is necessary to program two
NOP’s to allow clock resynchronization upon return from the
IDLE mode. The NOP’s are placed either at the beginning of
the IDLE Timer interrupt routine or immediately following the
“enter IDLE mode” instruction.
For more information on the IDLE Timer and its associated
interrupt, see the description in the Timers section.
7.4 DUAL CLOCK MODE OPERATION
This mode of operation allows for high speed operation of
the Core clock and low speed operation of the Idle Timer.
This mode can be entered from either the High Speed mode
or the Low Speed mode.
To enter from the High Speed mode, the following sequence
must be followed:
1. Software sets the LSON bit to 1.
2. Software waits until the low speed oscillator has stabi-
3. Software sets the DCEN bit to 1.
To enter from the Low Speed mode, the following sequence
must be followed:
1. Software sets the HSON bit to 1.
2. Software waits until the high speed oscillator has stabi-
lized. See Table 4 .
lized. See Table 4, Startup Times.
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