cop8cde9 National Semiconductor Corporation, cop8cde9 Datasheet - Page 45

• Manufacturer Part Number: cop8cde9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, 10-bit A/d And Brownout Reset
• Manufacturer: National Semiconductor Corporation

9.0 A/D Converter
9.1 OPERATING MODES
It supports both Single Ended and Differential modes of
operation.
Two specific analog channel selection modes are supported.
These are as follows:
1. Allow any specific channel to be selected at one time.
2. Allow any differential channel pair to be selected at one
In both Single Ended and Differential modes, there is the
capability to connect the analog multiplexor output and A/D
converter input to external pins. This provides the ability to
externally connect a common filter/signal conditioning circuit
for the A/D Converter.
The A/D Converter is supported by three memory mapped
registers: two result registers and the control register. When
the device is reset, the mode control register (ENAD) is
cleared, the A/D is powered down and the A/D result regis-
ters have unknown data.
9.1.1 A/D Control Register
The control register, ENAD, contains 4 bits for channel se-
lection, 1 bit for mode selection, 1 bit for the multiplexor
output selection, 1 bit for prescaler selection, and a Busy bit.
ADCH3
The A/D Converter performs the specific conversion re-
quested and stops.
time. The A/D Converter performs the specific differen-
tial conversion requested and stops.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TABLE 21. A/D Converter Channel Selection when the Multiplexor Output is Disabled
ADCH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Select Bits
(Continued)
ADCH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ADCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
45
Single Ended Mode
An A/D conversion is initiated by setting the ADBSY bit in the
ENAD control register. The result of the conversion is avail-
able to the user in the A/D result registers, ADRSTH and
ADRSTL, when ADBSY is cleared by the hardware on
completion of the conversion.
CHANNEL SELECT
This 4-bit field selects one of sixteen channels to be the V
The mode selection and the mux output determine the V
input. When MUX = 0, all sixteen channels are available, as
shown in Table 21 . When MUX = 1, only fourteen channels
are available, as shown in Table 22 .
All port pins which are used, in the application, in A/D opera-
tions must be configured as high-impedance inputs. If the
ports are configured as outputs or inputs with weak pull-up
there will be a conflict between the analog signal and the
digitally driven output.
ADCH3 ADCH2 ADCH1 ADCH0
Bit 7
Mode Select
Channel No.
ADMOD = 0
10
12
13
14
15
11
Channel Select
0
1
2
3
4
5
6
7
8
9
TABLE 20. ENAD
Channel Pairs (+, −)
Differential Mode
Mode Select
ADMOD = 1
Mode Select Mux/Out Prescale
ADMOD
12, 13
13, 12
14, 15
15, 14
10, 11
11, 10
0, 1
1, 0
2, 3
3, 2
4, 5
5, 4
6, 7
7, 6
8, 9
9, 8
MUX
PSC
Mux Output
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Disabled
MUX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADBSY
Busy
Bit 0
IN+
IN-
.