cop888gw National Semiconductor Corporation, cop888gw Datasheet - Page 25

• Manufacturer Part Number: cop888gw
• Description: 8-bit Microcontroller With Pulse Train Generators And Capture Modules
• Manufacturer: National Semiconductor Corporation

UART Operation
with nine data bits per frame. There is no parity selection in
this framing format. For other framing formats XBIT9 is not
needed and the bit is PSEL0 used in conjunction with PSEL1
to select parity.
The frame formats for the receiver differ from the transmitter
in the number of Stop bits required. The receiver only re-
quires one Stop bit in a frame, regardless of the setting of the
Stop bit selection bits in the control register. Note that an
implicit assumption is made for full duplex UART operation
that the framing formats are the same for the transmitter and
receiver.
UART INTERRUPTS
The UART is capable of generating interrupts. Interrupts are
generated on Receive Buffer Full and Transmit Buffer Empty.
Both interrupts have individual interrupt vectors. Two bytes
of program memory space are reserved for each interrupt
vector. The two vectors are located at addresses 0xEC to
0xEF Hex in the program memory space. The interrupts can
be individually enabled or disabled using Enable Transmit
Interrupt (ETl) and Enable Receive Interrupt (ERl) bits in the
ENUI register.
(Continued)
FIGURE 17. UART BAUD Clock Divisor Registers
FIGURE 16. UART BAUD Clock Generation
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The interrupt from the Transmitter is set pending, and re-
mains pending, as long as both the TBMT and ETl bits are
set. To remove this interrupt, software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit).
The interrupt from the receiver is set pending, and remains
pending, as long as both the RBFL and ERI bits are set. To
remove this interrupt, software must either clear the ERl bit
or read from the RBUF register (thus clearing the RBFL bit).
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the UART can be individually selected to come either from
an external source at the CKX pin (port L, pin L1) or from a
source selected in the PSR and BAUD registers. Internally,
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1–16 (in-
crements of 0.5) prescaler and an 11-bit binary counter
( Figure 16 ). The divide factors are specified through two
read/write registers shown in Figure 17 . Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Reg-
ister (PSR). PSR is cleared upon reset.
DS012065-19
DS012065-18
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