cop888gw National Semiconductor Corporation, cop888gw Datasheet - Page 24

• Manufacturer Part Number: cop888gw
• Description: 8-bit Microcontroller With Pulse Train Generators And Capture Modules
• Manufacturer: National Semiconductor Corporation

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UART Operation
SYNCHRONOUS MODE
In this mode data is transferred synchronously with the
clock. Data is transmitted on the rising edge and received on
the falling edge of the synchronous clock.
This mode is selected by setting SSEL bit in the ENUI
register. The input frequency to the UART is the same as the
baud rate.
When an external clock input is selected at the CKX pin, data
transmit and receive are performed synchronously with this
clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX pin as
clock output, the device generates the synchronous clock
output at the CKX pin. The internal baud rate generator is
used to produce the synchronous clock. Data transmit and
receive are performed synchronously with this clock.
FRAMING FORMATS
The UART supports several serial framing formats ( Figure
15 ). The format is selected using control bits in the ENU,
ENUR and ENUI registers.
For any of the above framing formats, the last Stop bit can
be programmed to be 7/8th of a bit in length. If two Stop bits
are selected and the 7/8th bit is set (selected), the second
Stop bit will be 7/8th of a bit in length.
The parity is enabled/disabled by PEN bit located in the ENU
register. Parity is selected for 7- and 8-bit modes only. If
(Continued)
FIGURE 15. Framing Formats
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The first format (1,1a, 1b, 1c) for data transmission (CHL0 =
1, CHL1 = 0) consists of Start bit, seven Data bits (excluding
parity) and 7/8, one or two Stop bits. In applications using
parity, the parity bit is generated and verified by hardware.
The second format (CHL0 = 0, CHL1 = 0) consists of one
Start bit, eight Data bits (excluding parity) and 7/8, one or
two Stop bits. Parity bit is generated and verified by hard-
ware.
The third format for transmission (CHL0 = 0, CHL1 = 1)
consists of one Start bit, nine Data bits and 7/8, one or two
Stop bits. This format also supports the UART “ATTENTION”
feature. When operating in this format, all eight bits of TBUF
and RBUF are used for data. The ninth data bit is transmitted
and received using two bits in the ENU and ENUR registers,
called XBIT9 and RBIT9. RBIT9 is a read only bit. Parity is
not generated or verified in this mode.
parity is enabled (PEN = 1), the parity selection is then
performed by PSEL0 and PSEL1 bits located in the ENU
register.
Note that the XBIT9/PSEL0 bit located in the ENU register
serves two mutually exclusive functions. This bit programs
the ninth bit for transmission when the UART is operating
DS012065-17