cop888gw National Semiconductor Corporation, cop888gw Datasheet
cop888gw
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cop888gw Summary of contents
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... National Semiconduc- 2 tor’s M CMOS ™ process technology. The COP888GW is a member of this expandable 8-bit core processor family of microcontrollers fully static part, fabricated using double-metal silicon gate microCMOS technology. Features include an 8-bit memory mapped architecture, ...
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... Block Diagram Connection Diagram www.national.com FIGURE 1. COP888GW Block Diagram Top View Order Number COP888GW-XXX/V See NS Package Number V68A 2 DS012065-1 DS012065-2 ...
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... Absolute Maximum Ratings SuppIy Voltage ( Voltage at Any Pin Total Current into V Pin (Source Electrical Characteristics COP888GW: −40˚C T 85˚C unless otherwise specified A Parameter Operating Voltage Power Supply Ripple (Note 2) Supply Current (Note 3) CKI = 10 MHz CKI = 4 MHz HALT Current (Note 4) ...
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... AC Electrical Characteristics COP888GW: −40˚C T 85˚C unless otherwise specified A Parameter Instruction Cycle Time ( Crystal, Resonator Ceramic CKI Clock Duty Cycle (Note 6) Rise Time (Note 6) Fall Time (Note 6) Inputs t SETUP t HOLD Output Propagation Delay (Note PD1 PD0 SO, SK All Others MICROWIRE ™ ...
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Typical Performance Characteristics Port D Source Current DS012065-23 Ports C/G/L/E/F Source Current DS012065-25 Ports C/G/L/E/F Weak Pull-Up Source Current DS012065-27 Idle — DS012065-29 Port D Sink Current DS012065-24 Ports C/G/L/E/F Sink Current DS012065-26 Dynamic — ...
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Pin Descriptions V and GND are the power supply pins. All V CC pins must be connected. CKI is the clock input. This comes from an R/C generated oscillator crystal oscillator (in conjunction with CKO). See Oscillator Description ...
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Pin Descriptions (Continued) Since input only pin and G7 is dedicated CKO clock output pin, the associated bits in the data and configuration registers for G6 and G7 are used for special purpose func- tions as outlined ...
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Functional Description The data memory consists of 512 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement ...
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Data Memory Segment RAM Extension Note 10: Reads as all ones. Reset This device enters a reset state immediately upon detecting a logic low on the RESET pin. The RESET pin must be held low for a minimum of one ...
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Reset (Continued) WKEN, WKEDG: CLEARED WKPND: RANDOM S Register: CLEARED SP (Stack Pointer): Loaded with 6F Hex B and X Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on RAM: UNAFFECTED after RESET with power already ...
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Control Registers (Continued) T0EN Timer T0 Interrupt Enable (Bit 12 toggle) T0PND Timer T0 Interrupt pending LPEN L Port Interrupt Enable (Multi-Input Wake up/ Interrupt) Bit 7 could be used as a flag Unused LPEN T0PND T0EN WPND WEN Bit ...
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Timers (Continued) www.national.com FIGURE 7. Timer in PWM Mode FIGURE 8. Timer in External Event Counter Mode 12 DS012065-8 DS012065-9 ...
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Timers (Continued) In this mode the input pin TxB can be used as an indepen- dent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is ...
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Capture Timer (Continued) may be stopped/started under software control, and each capture timer may be configured to interrupt the microcon- troller on an underflow or input capture. TxC3 TxC2 TxC1 Timer Mode MODE 2 (External Event Counter) ...
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Capture Timer (Continued) The registers shown in the block diagram include those for Capture Timer 1 (CM1), as well as, the capture timer 1 control register. These registers are read/writable (with the exception of the capture registers, which are read-only) ...
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Capture Timer (Continued) interrupts should not be disabIed prior to stopping the timer. If interrupts are not being used, the user should poll the capture timer pending bits after stopping the timer. If the user wishes to ignore this capture ...
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Pulse Train Generators The four 8-bit registers shown in each individual counter in the block diagram constitute a 16-bit prescaler and a 16-bit count register. These registers are all read/writable and may be accessed through the data memory address/data bus. ...
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Pulse Train Generators erated before the output is toggled. The user may also choose to alter the logic level on the port pin before restart- ing. This is done by initializing the associated port pin data register bit. A counter ...
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Multiply/Divide (Continued) Register Name Multiplication Assignment (Address) Before Operation MDR1 (xx98) Unused MDR2 (xx99) Multiplier MDR3 (xx9A) MDR4 (xx9B) Low byte of multiplicand MDR5 (xx9C) High byte of multiplicand CONTROL REGISTER BITS The Multiply/Divide control register (MDCR) is located at ...
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Power Save Modes (Continued) The devices have two mask options associated with the HALT mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT mode. With the HALT mode enable mask option, ...
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Multi-Input Wakeup (Continued) This selection is made via the register WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition negative edge ...
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UART (Continued) UART CONTROL AND STATUS REGISTERS The operation of the UART is programmed through three registers: ENU, ENUR and ENUI. The function of the indi- vidual bits in these registers is as follows: ENU-UART Control and Status Register (Address ...
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UART (Continued) PEN: This bit enables/disables Parity (7- and 8-bit modes only). PEN = 0 Parity disabled. PEN = 1 Parity enabled. ENUR — UART RECEIVE CONTROL AND STATUS REGISTER RCVG: This bit is set high whenever a framing error ...
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UART Operation (Continued) SYNCHRONOUS MODE In this mode data is transferred synchronously with the clock. Data is transmitted on the rising edge and received on the falling edge of the synchronous clock. This mode is selected by setting SSEL bit ...
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UART Operation (Continued) with nine data bits per frame. There is no parity selection in this framing format. For other framing formats XBIT9 is not needed and the bit is PSEL0 used in conjunction with PSEL1 to select parity. The ...
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Baud Clock Generation As shown in Table Prescaler Factor of 0 corresponds to NO CLOCK. This condition is the UART power down mode where the UART clock is turned off for power saving pur- pose. The user ...
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Baud Clock Generation As an example, considering Asynchronous Mode and a CKI clock of 4.608 MHz, the prescaler factor selected is: 4.608/1.8432 = 2.5 The 2.5 entry is available in Table 5 . The 1.8432 MHz prescaler output is then ...
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Interrupts (Continued) pending bits are set. If GlE = 1 and an interrupt is active, then the processor will be interrupted as soon ready to start executing an instruction except if the above condi- tions happen during ...
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Interrupts (Continued) VIS and the vector table must be located in the same 256-byte block (0y00 to 0yFF) except if VIS is located at the last address of a block. In this case, the table must be in the next ...
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Detection of Illegal Conditions The device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading of undefined ROM gets zeroes. The opcode for software interrupt is 00. If the program ...
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MICROWIRE/PLUS (Continued) MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to ...
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Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. ADDRESS S/ADD REG 0000 to 006F 0070 to 007F xx80 to xx8F xx90 xx91 xx92 xx93 xx94 xx95 xx96 xx97 xx98 xx99 ...
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Memory Map (Continued) ADDRESS S/ADD REG xxBA xxBB xxBC xxBD xxBE xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD to xxCF xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA xxDB ...
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Memory Map (Continued) ADDRESS S/ADD REG xxFE xxFF 0100 to 017F 0200 to 027F 0300 to 037F Reading memory locations 0070H-007FH (Segment 0) will return all ones. Reading unused memory locations between 0080H-00F0 Hex (Segment 0) will return undefined data. ...
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Instruction Set (Continued) Symbols [B] Memory Indirectly Addressed by B Register [X] Memory Indirectly Addressed by X Register MD Direct Addressed Memory Mem Direct Addressed Memory or [B] Meml Direct Addressed Memory or [B] or Immediate Data INSTRUCTION SET ADD ...
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Instruction Set (Continued) IFNC IF Not C POP A POP the stack into A PUSH A PUSH A onto the stack VIS Vector to Interrupt Service Routine JMPL Addr. Jump absolute Long JMP Addr. Jump absolute JP Disp. Jump relative ...
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Instruction Execution Time Transfer of Control Instructions Memory Transfer Instructions Register Indirect [B] [ (Note 13) 1/1 1 (Note 13) 1/1 1 Imm LD B, Imm LD Mem, Imm 2/2 LD Reg, Imm IFEQ ...
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Note: The opcode 60 Hex is also the opcode for IFBIT, # iA. www.national.com Nibble Lower 38 ...
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Development Support SUMMARY • iceMASTER ™ : IM-COP8/400 — Full feature in-circuit emulation for all COP8 products. A full set of COP8 Basic and Feature Family device and package specific probes are available. • COP8 Debug Module: Moderate cost in-circuit ...
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Development Support iceMASTER DEBUG MODULE (DM) The iceMASTER Debug Module based, combination in-circuit emulation tool and COP8 based OTP/EPROM pro- gramming tool developed and marketed by MetaLink Corpo- ration to support the whole COP8 family of products. ...
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... North Europe America +49-8152-4183 +49-8856-932616 +44-0734-440011 Call Asia +44-1226-767404 Fax: 0-1226-370-434 +49-80 9156 96-0 Fax: +49-80 9123 86 +41-1-9450300 41 Clock Package Emulates Option 68 COP888GW HALT PLCC En Asia +852-234-16611 +852-2710-8121 Call North America +886-2-764-0215 Fax: +886-2-756-6403 +852-737-1800 +886-2-917-3005 Fax: +886-2-911-1283 www.national.com ...
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Development Support AVAILABLE LITERATURE For more information, please see the COP8 Basic Family User’s Manual, Literature Number 620895, COP8 Feature Family User’s Manual, Literature Number 620897 and Na- tional’s Family of 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009. DIAL-A-HELPER ...
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Development Support (Continued) DIAL-A-HELPER via a WorldWide Web Browser ftp://nscmicro.nsc.com National Semiconductor on the WorldWide Web See us on the WorldWide Web at: http://www.national.com CUSTOMER RESPONSE CENTER Complete product information and technical support is avail- able from National’s customer response ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted 68-Lead Molded Plastic Chip Carrier Order Number COP888GW-XXX/V NS Package Number V68A 2. A critical component is any component of a life ...