cop888gw National Semiconductor Corporation, cop888gw Datasheet - Page 23

• Manufacturer Part Number: cop888gw
• Description: 8-bit Microcontroller With Pulse Train Generators And Capture Modules
• Manufacturer: National Semiconductor Corporation

UART
PEN: This bit enables/disables Parity (7- and 8-bit modes
only).
PEN = 0
PEN = 1
ENUR — UART RECEIVE CONTROL AND STATUS
REGISTER
RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high.
XMTG: This bit is set to indicate that the UART is transmit-
ting. It gets reset at the end of the last frame (end of last Stop
bit).
ATTN: ATTENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character with
data bit nine set.
RBIT9: Contains the ninth data bit received when the UART
is operating with nine data bits per frame.
SPARE: Reserved for future use.
PE: Flags a Parity Error.
PE = 0
PE = 1
FE: Flags a Framing Error.
FE = 0
FE = 1
DOE: Flags a Data Overrun Error.
DOE = 0
DOE = 1
ENUI — UART INTERRUPT AND CLOCK SOURCE
REGISTER
ETI: This bit enables/disables interrupt from the transmitter
section.
ETI = 0
ETI = 1
ERI: This bit enables/disables interrupt from the receiver
section.
ERI = 0
ERI = 1
XTCLK: This bit selects the clock source for the transmitter
section.
XTCLK = 0
XTCLK = 1
XRCLK: This bit selects the clock source for the receiver
section.
XRCLK = 0
XRCLK = 1
SSEL: UART mode select.
SSEL = 0
SSEL = 1
ETDX: TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
Indicates no Parity Error has been detected since
the last time the ENUR register was read.
Indicates the occurrence of a Parity Error.
Indicates no Framing Error has been detected
since the last time the ENUR register was read.
Indicates the occurrence of a Framing Error.
Interrupt from the transmitter is disabled.
Interrupt from the transmitter is enabled.
Interrupt from the receiver is disabled.
Interrupt from the receiver is enabled.
(Continued)
Parity disabled.
Parity enabled.
Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register was
read.
Indicates the occurrence of a Data Overrun Er-
ror.
Asynchronous Mode.
Synchronous Mode.
The clock source is selected through the PSR
and BAUD registers.
Signal on CKX (L1) pin is used as the clock.
The clock source is selected through the PSR
and BAUD registers.
Signal on CKX (L1) pin is used as the clock.
23
To simulate line break generation, software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers.
STP78: This bit is set to program the last Stop bit to be 7/8th
of a bit in length.
STP2: This bit programs the number of Stop bits to be trans-
mitted.
STP2 = 0
STP2 = 1
Associated I/O Pins
Data is transmitted on the TDX pin and received on the RDX
pin. TDX is the alternate function assigned to Port L pin L2;
it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function of Port L pin L3, requiring no
setup.
The baud rate clock for the UART can be generated on-chip,
or can be taken from an external source. Port L pin L1 (CKX)
is the external clock I/O pin. The CKX pin can be either an
input or an output, as determined by Port L Configuration
and Data registers (Bit 1). As an input, it accepts a clock
signal which may be selected to drive the transmitter and/or
receiver. As an output, it presents the internal Baud Rate
Generator output.
UART Operation
The UART has two modes of operation: asynchronous mode
and synchronous mode.
ASYNCHRONOUS MODE
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
The TSFT and TBUF registers double-buffer data for trans-
mission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmit-
ting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a read/write register.
The RSFT and RBUF registers double-buffer data being
received. The UART receiver continually monitors the signal
on the RDX pin for a low level to detect the beginning of a
Start bit. Upon sensing this low level, it waits for half a bit
time and samples again. If the RDX pin is still low, the
receiver considers this to be a valid Start bit, and the remain-
ing bits in the character frame are each sampled a single
time, at the mid-bit position. Serial data input on the RDX pin
is shifted into the RSFT register. Upon receiving the com-
plete character, the contents of the RSFT register are copied
into the RBUF register and the Received Buffer Full Flag
(RBFL) is set. RBFL is automatically reset when software
reads the character from the RBUF register. RBUF is a read
only register. There is also the RCVG bit which is set high
when a framing error occurs and goes low once RDX goes
high. TBMT, XMTG, RBFL and RCVG are read only bits.
One Stop bit transmitted.
Two Stop bits transmitted.
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