mc9s08ac16 Freescale Semiconductor, Inc, mc9s08ac16 Datasheet - Page 98
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mc9s08ac16
Manufacturer Part Number
mc9s08ac16
Description
Hcs08 Microcontrollers 8-bit Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08AC16.pdf
(338 pages)
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Chapter 6 Parallel Input/Output
6.7.7
Port D parallel I/O function is controlled by the registers listed below.
98
PTDDD[3:0]
Bits 7 through 4 are reserved bits that must always be written to 0.
Bits 7 through 4 are reserved bits that must always be written to 0.
PTDD[3:0]
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
Port D I/O Registers (PTDD and PTDDD)
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
R
R
0
0
7
7
R
R
0
0
6
6
Figure 6-26. Data Direction for Port D (PTDDD)
Table 6-17. PTDDD Register Field Descriptions
Table 6-16. PTDD Register Field Descriptions
Figure 6-25. Port D Data Register (PTDD)
MC9S08AC16 Series Data Sheet, Rev. 0
R
R
0
0
5
5
PRELIMINARY
R
R
0
0
4
4
Description
Description
PTDDD3
PTDD3
3
0
3
0
PTDDD2
PTDD2
1
0
0
2
2
1
PTDDD1
Freescale Semiconductor
PTDD1
0
0
1
1
PTDDD0
PTDD0
0
0
0
0
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