mc9s08ac16 Freescale Semiconductor, Inc, mc9s08ac16 Datasheet - Page 192

no-image

mc9s08ac16

Manufacturer Part Number
mc9s08ac16
Description
Hcs08 Microcontrollers 8-bit Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc9s08ac16CFGE
Manufacturer:
FREESCAL
Quantity:
4 000
Part Number:
mc9s08ac16CFGE
Manufacturer:
FREESCALE
Quantity:
5 800
Part Number:
mc9s08ac16CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s08ac16CFGE
Manufacturer:
FREESCALE
Quantity:
5 800
Part Number:
mc9s08ac16CFGE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc9s08ac16CFGE
0
Part Number:
mc9s08ac16CFGER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s08ac16CFJE
Manufacturer:
FREESCALE
Quantity:
5 375
Part Number:
mc9s08ac16MFGE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc9s08ac16MFJE
Manufacturer:
FREESCALE
Quantity:
20 000
Chapter 10 Timer/PWM Module (S08TPMV3)
10.8.2.1.2
When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to
down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF
corresponds to the end of a PWM period.
10.8.2.2
The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare,
edge-aligned PWM, or center-aligned PWM).
10.8.2.2.1
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select no edge
(off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described
in
10.8.2.2.2
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step
sequence described
10.8.2.2.3
For channels configured for PWM operation there are two possibilities. When the channel is configured
for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register
which marks the end of the active duty cycle period. When the channel is configured for center-aligned
PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM
case, the channel flag is set at the start and at the end of the active duty cycle period which are the times
when the timer counter matches the channel value register. The flag is cleared by the two-step sequence
described
192
Section 10.8.2, “Description of Interrupt Operation.”
Section 10.8.2, “Description of Interrupt Operation.”
Channel Event Interrupt Description
Center-Aligned PWM Case
Input Capture Events
Output Compare Events
PWM End-of-Duty-Cycle Events
Section 10.8.2, “Description of Interrupt Operation.”
MC9S08AC16 Series Data Sheet, Rev. 0
PRELIMINARY
Freescale Semiconductor

Related parts for mc9s08ac16