mc9s08ac16 Freescale Semiconductor, Inc, mc9s08ac16 Datasheet - Page 238

• Manufacturer Part Number: mc9s08ac16
• Description: Hcs08 Microcontrollers 8-bit Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 13 Inter-Integrated Circuit (S08IICV2)
13.3.5
In slave mode, the same functions are available after an address match has occurred.
The TX bit in IIC1C must correctly reflect the desired direction of transfer in master and slave modes for
the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is
desired, reading the IIC1D does not initiate the receive.
Reading the IIC1D returns the last byte received while the IIC is configured in master receive or slave
receive modes. The IIC1D does not reflect every byte transmitted on the IIC bus, nor can software verify
that a byte has been written to the IIC1D correctly by reading it back.
In master transmit mode, the first byte of data written to IIC1D following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required
R/W bit (in position bit 0).
13.3.6
238
Reset
Reset
Field
DATA
7–0
W
W
R
R
GCAEN
IIC Data I/O Register (IIC1D)
IIC Control Register 2 (IIC1C2)
Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
0
0
7
7
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IIC1D register to prevent an inadvertent
initiation of a master receive data transfer.
= Unimplemented or Reserved
ADEXT
0
0
6
6
Figure 13-8. IIC Control Register (IIC1C2)
Figure 13-7. IIC Data I/O Register (IIC1D)
Table 13-7. IIC1D Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 0
0
0
0
5
5
PRELIMINARY
NOTE
0
0
0
4
4
Description
DATA
3
0
3
0
0
AD10
0
0
2
2
Freescale Semiconductor
AD9
0
0
1
1
AD8
0
0
0
0