atxmega128a3-mu ATMEL Corporation, atxmega128a3-mu Datasheet - Page 35

• Manufacturer Part Number: atxmega128a3-mu
• Description: 8/16-bit Xmega Microcontroller
• Manufacturer: ATMEL Corporation

23. ADC - 12-bit Analog to Digital Converter
23.1
23.2
8068A–AVR–02/08
Features
Overview
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The XMEGA A3 devices has two Analog to Digital Converters (ADC), see
36. The two ADCs modules can be operated simultaneously, individually or synchronized.
The ADC converts analog voltages to digital values.The ADC has 12-bit resolution and is capa-
ble of converting up to 2 million samples per second. The input selection is flexible, and both
single-ended and differential measurements can be done. The ADC provides both signed and
unsigned results, and an optional gain stage is available to increase the dynamic range of the
ADC.
The ADC uses Successive Approximation Result (SAR) ADC. A SAR ADC measures one bit of
the conversion result a time. The ADC has a pipeline architecture. This means that a new analog
voltage can be sampled and a new ADC measurement started while other ADC measurements
are ongoing.
ADC measurements can either be started by the application software or an incoming event from
another peripheral in the device. Four different result registers with individual channel selection
(MUX registers) are provided to make it easier for the application to keep track of the data. It is
also possible to use DMA to move ADC results directly to memory or peripherals.
Both internal and external analog reference voltages can be used. A very accurate internal 1.0V
reference is available, providing a conversion range from 0 - 1.0 V in unsigned mode and -1.0 to
1.0V in signed mode.
Two ADCs with 12-bit resolution
2 Msps conversion rate
Signed- and Unsigned conversions
4 result registers with individual channel control for each ADC
16 single ended inputs
16x8 differential inputs
Gain of 1, 2, 4, 8, 16, 32 or 64
Selectable accuracy of 8-, 10- or 12-bit.
Built-in Auto Calibration
Internal- or External Reference
Event triggered conversion for accurate timing
DMA transfer of conversion results
Interrupt/Event on compare result
ATxmega A3
Figure 23-1 on page
35