at32ap7002 ATMEL Corporation, at32ap7002 Datasheet - Page 42

• Manufacturer Part Number: at32ap7002
• Description: Avr 32 32-bit Microcontroller
• Manufacturer: ATMEL Corporation

32054DS–AVR32–10/07
12. PWM update period to a 0 value does not work
13. PWM channel status may be wrong if disabled before a period has elapsed
14. TWI transfer error without ACK
15. SSC can not transmit or receive data
16. USART - RXBREAK flag is not correctly handled
17. USART - Manchester encoding/decoding is not working.
18. SPI - Disabling SPI has no effect on TDRE flag.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit
for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if
the channel was disabled before the period elapsed. It will then read '0' as expected.
Fix/Workaround
Reading the PWM channel status of a disabled channel is only correct after a PWM period
If the TWI does not receive an ACK from a slave during the address+R/W phase, no bits in
the status register will be set to indicate this. Hence, the transfer will never complete.
Fix/Workaround
To prevent errors due to missing ACK, the software should use a timeout mechanism to ter-
minate the transfer if this happens.
The SSC can not transmit or receive data when CKS = CKDIV and CKO = none in TCMR or
RCMR respectively.
Fix/Workaround
Set CKO to a value that is not "None" and enable the PIO with output driver disabled on the
TK/RK pin.
The FRAME_ERROR is set instead of the RXBREAK when the break character is located
just after the STOP BIT(S) in ASYNCHRONOUS mode.
Fix/Workaround
The transmitting UART must set timeguard greater than 0.
Manchester encoding/decoding is not working.
Fix/Workaround
Do not use manchester encoding.
Disabling SPI has no effect on TDRE whereas the write data command is filtered when SPI
is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset
the TDRE flag by writing in the SPI_TDR. So if the SPI is disabled during a PDC transfer, the
AT32AP7002
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