at32ap7002 ATMEL Corporation, at32ap7002 Datasheet - Page 41

• Manufacturer Part Number: at32ap7002
• Description: Avr 32 32-bit Microcontroller
• Manufacturer: ATMEL Corporation

32054DS–AVR32–10/07
5. MMC data write operation with less than 12 bytes is impossible.
6. MMC SDIO interrupt only works for slot A
7. PSIF TXEN/RXEN may disable the transmitter/receiver
8. PSIF TXRDY interrupt corrupts transfers
9. LCD memory error interupt does not work
10. PWM counter restarts at 0x0001
11. PWM channel interrupt enabling triggers an interrupt
MCI data write operation with less than 12 bytes is impossible. The Data Write operation
with a number of bytes less than 12 leaves the internal MCI FIFO in an inconsistent state.
Subsequent reads and writes will not function properly.
Fix/Workaround
Always transfer 12 or more bytes at a time. If less than 12 bytes are transferred, the only
recovery mechanism is to perform a software reset of the MCI.
If 1-bit data bus width and on other slots than slot A, the SDIO interrupt can not be cap-
tured.
Fix/Workaround
Use slot A.
Writing a '0' to RXEN will disable the receiver. Writing '0' to TXEN will disable the transmitter.
Fix/Workaround
When accessing the PS/2 Control Register always write '1' to RXEN to keep the receiver
enabled, and write '1' to TXEN to keep the transmitter enabled.
When writing to the Transmit Holding Register (THR), the data will be transferred to the data
shift register immediately, regardless of the state of the data shift register. If a transfer is
ongoing, it will be interrupted and a new transfer will be started with the new data written to
THR.
Fix/Workaround
Use the TXEMPTY-interrupt instead of the TXRDY-interrupt to update the THR. This
ensures that a transfer is completed.
Writing to the MERIT-bit in the LCD Interrupt Test Register (ITR) does not cause an interrupt
as intended. The MERIC-bit in the LCD Interrupt Clear Register (ICR) cannot be written.
This means that if the MERIS-bit in ISR is set, it cannot be cleared.
Fix/Workaround
Memory error interrupt should not be used.
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
AT32AP7002
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