at32ap7002 ATMEL Corporation, at32ap7002 Datasheet
at32ap7002
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at32ap7002 Summary of contents
Page 1
... Sample rates kHz • On-Chip Debug System – Nexus Class 3 – Full speed, non-intrusive data and program trace – Runtime control and JTAG interface • Package/Pins – AT32AP7002: 196-ball CTBGA • Power supplies – 1.65V to1.95V VDDCORE – 3.0V to 3.6V VDDIO ® 32 32-Bit Microcontroller ® ...
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... AT32AP7002 also features an onboard LCD Controller, supporting single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays gray shades are supported using a time-based dither- ing algorithm and Frame Rate Control (FRC) method ...
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... AT32AP7002 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The C-compiler is closely linked to the architecture and is able to utilize code optimization fea- tures, both for size and speed. 32054DS–AVR32–10/07 ...
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... DMA CONTROLLER AUDIO BITSTREAM DAC MULTIMEDIA CARD INTERFACE AC97 CONTROLLER POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER TIMER/COUNTER 0/1 EXTERNAL INTERRUPT CONTROLLER AT32AP7002 PIXEL COPROCESSOR VSYNC, DATA HSYNC, CACHE LCD PWR, PCLK, CONTRO MODE, LLER DVAL, CC, DATA[22..0], GPL[7.. DMA M ...
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... Supports packed and planar input and output formats. • Supports subsampled input color spaces (i.e 4:2:2, 4:2:0). • Configurable Filter Coefficients. • Throughput of one sample per cycle for a 9-tap FIR filter. • Can use the built-in accumulator to extend the FIR filter to more than 9-taps. • Can be used for bilinear/bicubic interpolations. AT32AP7002 5 ...
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... HSB bus matrix with 10 Masters and 8 Slaves handled – Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller, LCD Controller, DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM EBI and, USB. 32054DS–AVR32–10/07 AT32AP7002 6 ...
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... Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the HSB bus, and which DMA controller is connected to which peripheral. 32054DS–AVR32–10/07 AT32AP7002 Figure 4-1 on page 13. All modules connected to the accessed default ...
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... VDDIO GND PA12 PA16 GND PA19 GND VDDIO PA23 PD17 AVDDUSB PD12 PD15 PD16 PD13 PD14 XIN1 AT32AP7002 BOTTOM VIEW PC23 PC20 XIN32 PC22 XOUT32 PC29 XOUT0 AGNDOSC AVDDOSC OSCEN_N TDI RESET_N PA02 ...
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... PB13 PB00 PX44 GND PX43 PX31 VDDIO PX28 PX29 PX23 PX27 PX36 PX19 PX07 VDDIO PX11 PX12 PX09 PB29 PX52 PX08 AT32AP7002 13 14 PB05 PB04 PB06 PB03 PB07 PB02 GND PB01 VDDIO PX45 PX46 PX40 VDDCORE PX39 VDDCORE PX26 PX21 PX24 ...
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... Power Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators, and PLL’s Analog Analog Analog JTAG Input Input Output Input Input Auxiliary Port - AUX Output Output Output Input AT32AP7002 Active Level Comments 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 3.0 to 3.6V Low Low 10 ...
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... Input AC97 Controller - AC97C Input Output Output Input Audio Bitstream DAC - ABDAC Output Output External Bus Interface - EBI I/O Output Output Output Output Output I/O Output Output Output AT32AP7002 Active Level Comments Low Low Low Low Low Low Low Low Low Low Low 11 ...
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... Output Output Output Output Output Image Sensor Interface - ISI Input Input Input Input LCD Controller - LCDC Output Input Output Output Output Output Output Output Output MultiMedia Card Interface - MCI Output I/O AT32AP7002 Active Level Comments Low Low Low Low Low Low Low 12 ...
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... Channel 2 Line A B0 Channel 0 Line B 32054DS–AVR32–10/07 Type Parallel Input/Output - PIOA, PIOB, PIOC, PIOD PS2 Interface - PSIF Serial Peripheral Interface - SPI0, SPI1 Output Synchronous Serial Controller - SSC0, SSC1, SSC2 Output DMA Controller - DMACA Timer/Counter - TIMER0, TIMER1 AT32AP7002 Active Level Comments I/O I/O I/O I/O I/O Input I/O I/O I/O ...
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... Type I/O I/O Input Input Input Two-wire Interface - TWI I/O I/O I/O Input Output Input Output Pulse Width Modulator - PWM Output USB Interface - USBA Analog Analog Analog Analog Analog AT32AP7002 Active Level Comments Connected to a 6810 Ohm ± 0.5% resistor to gound and capacitor to ground. 14 ...
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... Power Considerations 4.1 Power Supplies The AT32AP7002 has several types of power supply pins: • VDDCORE pins: Power the core, memories, and peripherals. Voltage is 1.8V nominal. • VDDIO pins: Power I/O lines. Voltage is 3.3V nominal. • VDDPLL pin: Powers the PLL. Voltage is 1.8V nominal. • VDDUSB pin: Powers the USB. Voltage is 1.8V nominal. ...
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... All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, I/O lines default as inputs with pull-up resistors enabled, except when indicated otherwise in the column “Reset State” of the PIO Controller multiplexing tables. 32054DS–AVR32–10/07 AT32AP7002 16 ...
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... Physical Memory Map The system bus is implemented as an HSB bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AT32AP7002 by default uses segment translation, as described in the AVR32 Architecture Manual. The 32 bit physical address space is mapped as follows: Table 6-1 ...
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... Table 6-3. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 32054DS–AVR32–10/07 HSB masters HSB slaves AT32AP7002 CPU Dcache CPU Icache HSB-HSB Bridge ISI DMA USBA DMA LCD Controller DMA DMAC Master Interface 0 DMAC Master Interface 1 Internal SRAM 0 Internal SRAM1 PBA ...
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... Synchronous Serial Controller - SSC0 SSC1 Synchronous Serial Controller - SSC1 SSC2 Synchronous Serial Controller - SSC2 PIOA Parallel Input/Output 2 - PIOA PIOB Parallel Input/Output 2 - PIOB PIOC Parallel Input/Output 2 - PIOC PIOD Parallel Input/Output 2 - PIOD AT32AP7002 Bus HSB HSB HSB ...
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... AC97C AC97 Controller - AC97C ISI Image Sensor Interface - ISI USBA USB Configuration Interface - USBA SMC Static Memory Controller - SMC SDRAMC SDRAM Controller - SDRAMC ECC Error Correcting Code Controller - ECC AT32AP7002 Bus ...
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... Each group can have interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individ- ual submodules for a description of the semantic of the different interrupt requests. The interrupt request signals in AT32AP7002 are connected to the INTC as follows: Table 7-2. Group ...
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... Interrupt Request Signal Map Line Signal 0 EIC0 1 EIC1 2 EIC2 3 EIC3 RTC 0 TC00 1 TC01 2 TC02 0 TC10 1 TC11 2 TC12 0 PWM 0 ABDAC 0 MCI 0 AC97C 0 ISI 0 USBA 0 EBI Hardware Handshaking Connection AT32AP7002 Hardware Handshaking Interface ...
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... TIMER_CLOCK5 External XC0 XC1 XC2 Internal TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 USART clock connections Source Name Internal CLK_DIV AT32AP7002 Connection clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 7.7 clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32 See Section 7.7 Connection clk_pba / 8 23 ...
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... SPI clock connections Source Internal External Interrupt Pin Mapping Nexus OCD AUX port connections AXS=0 EVTI_N PB09 PB08 PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00 AT32AP7002 Name Connection CLK_DIV clk_pba / 32 Connection PB24 PB25 PB26 PB27 PB28 AXS=1 EVTI_N PC18 PC14 PC12 PC11 ...
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... Peripheral Multiplexing on IO lines The AT32AP7002 features five PIO controllers, PIOA to PIOE, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions The tables in the following pages define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers ...
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... PB24 NMI_N PB25 EXTINT0 PB26 EXTINT1 PB27 EXTINT2 PB28 EXTINT3 PB29 PM - GCLK[3] PB30 PM - GCLK[4] AT32AP7002 TC1 - B2 TC1 - CLK1 TC1 - CLK2 Peripheral B SPI1 - MISO SPI1 - MOSI SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - SCK MCI - CMD[1] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] ...
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... AT32AP7002 27 ...
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... LCDC - DATA[7] PD04 LCDC - DATA[10] PD05 LCDC - DATA[11] PD06 LCDC - DATA[12] PD07 LCDC - DATA[13] PD08 LCDC - DATA[14] PD09 LCDC - DATA[15] PD12 LCDC - DATA[18] PD13 LCDC - DATA[19] PD14 LCDC - DATA[20] PD15 LCDC - DATA[21] PD16 LCDC - DATA[22] PD17 LCDC - DATA[23] AT32AP7002 Peripheral B Peripheral B 28 ...
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... Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. 32054DS–AVR32–10/ – – – – – – – – – EBI_CS4A EBI_CS3A AT32AP7002 – – – – – – – – EBI_DBPUC – EBI_CS1A - 29 ...
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... EBI - DATA[14] EBI - DATA[15] EBI - ADDR[0] EBI - ADDR[1] EBI - ADDR[2] EBI - ADDR[3] EBI - ADDR[4] EBI - ADDR[5] EBI - ADDR[6] EBI - ADDR[7] EBI - ADDR[8] EBI - ADDR[9] EBI - ADDR[10] EBI - ADDR[11] EBI - ADDR[12] EBI - ADDR[13] EBI - ADDR[14] EBI - ADDR[15] AT32AP7002 The pull-up resistors are 30 ...
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... EBI - ADDR[18] EBI - ADDR[19] EBI - ADDR[20] EBI - ADDR[21] EBI - ADDR[22] EBI - NCS[0] EBI - NCS[1] EBI - NCS[3] EBI - NRD EBI - NWE0 EBI - NWE1 EBI - NWE3 EBI - SDCK EBI - SDCKE EBI - RAS EBI - CAS EBI - SDWE EBI - SDA10 EBI - NANDOE EBI - NANDWE AT32AP7002 31 ...
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... Programming Facilities – Word, Half-word, Byte Access – Automatic Page Break When Memory Boundary Has Been Reached – Multibank Ping-pong Access – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable 32054DS–AVR32–10/07 AT32AP7002 TM TM and CompactFlash Support TM Support ...
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... The chip select line may be left active to speed up transfers on the same device 7.8.6 Two-wire Interface • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations 32054DS–AVR32–10/07 AT32AP7002 ™ Devices with 8- or 16-bit Data Path. 33 ...
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... One RX and one TX channel for data transfers, connected to the DMACA • Time Slot Assigner allowing to assign time slots to a channel • Channels support mono or stereo bit sample length - Variable sampling rate AC97 Codec Interface (48KHz and below) 32054DS–AVR32–10/07 AT32AP7002 34 ...
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... Two independent Linear Dividers working on modulo n counter outputs • Independent channel programming – Independent Enable Disable Commands – Independent Clock – Independent Period and Duty Cycle, with Double Bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 32054DS–AVR32–10/07 AT32AP7002 35 ...
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... Controller for management of virtual Frame Buffer – Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer • Automatic resynchronization of the frame buffer pointer to prevent flickering • Configurable coefficients with flexible fixed-point representation. 32054DS–AVR32–10/07 AT32AP7002 36 ...
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... Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image 50 • Programmable frame capture rate 32054DS–AVR32–10/07 AT32AP7002 37 ...
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... Boot Sequence This chapter summarizes the boot sequence of the AT32AP7002. The behaviour after power-up is controlled by the Power Manager. 8.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset (POR) circuitry until the voltage has reached the power-on reset rising threshold value (see Electrical Character- istics for details) ...
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... Ordering Information Figure 9-1. Ordering Information Ordering Code AT32AP7002-CTUR AT32AP7002-CTUT 32054DS–AVR32–10/07 Package Package Type CTBGA196 Green CTBGA196 Green AT32AP7002 Temperature Packing Operating Range Reel Industrial (-40°C to 85°C) Tray Industrial (-40°C to 85°C) 39 ...
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... Select PS=1 and store data for PCS and LASTXFER for each data in transmit buffer. 4. SPI LASTXFER overrides Chip Select The LASTXFER bit overrides Chip Select input when and CSAAT is used. Fix/Workaround - Do not use the CSAAT - Use GPIO as Chip Select input - Select Transfer 32-bit with correct LASTXFER settings. 32054DS–AVR32–10/07 AT32AP7002 40 ...
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... PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 11. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. 32054DS–AVR32–10/07 AT32AP7002 41 ...
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... Disabling SPI has no effect on TDRE whereas the write data command is filtered when SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset the TDRE flag by writing in the SPI_TDR the SPI is disabled during a PDC transfer, the 32054DS–AVR32–10/07 AT32AP7002 42 ...
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... There UNDERRUN flag available, therefore in slave mode there is no way to be informed of a character lost in transmission. Fix/Workaround PDC/PDCA transfers: None. Manual transfers (no PDC and TX slave only): Read the RHR every time the THR is written. The OVRS flag of the status register will track any UNDERRUN on the TX side. 32054DS–AVR32–10/07 AT32AP7002 43 ...
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... Fix/Workaround Add external pulldown resistors (5 kΩ) on these lines if booting from a flash larger than 8 MB using these address lines. 28. SSC - Additional delay on TD output A delay from system clock cycles is added to TD output when: 32054DS–AVR32–10/07 AT32AP7002 44 ...
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... AVR32_PM.rcause register for WDT reset and use a GPIO pin to reset the system. This method requires that one of the GPIO pins are available and connected externally to the RESET_N pin. After the GPIO pin has pulled down the reset line the GPIO will be reset and leave the pin tristated with pullup. 32054DS–AVR32–10/07 AT32AP7002 45 ...
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... TDR by right aligning the useful value. This allows the number of bytes transferred into the TDR to match the number set up in the BCNT field of the MCI Block Register (BLKR). 10.2 Rev. B Not sampled. 10.3 Rev. A Not sampled. 32054DS–AVR32–10/07 AT32AP7002 46 ...
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... Rewritten the Register Configuration Guide and renamed it “Register Configuration Example“ in ”LCD Controller (LCDC)” on page 800. Updated formula for pixel clock in ”LCD Control Register 1” on page AT32AP7002 ”Peripherals” on page 75“. ”Peripherals” on page 75. 80. ”HSB Bus Matrix (HMATRIX)” on page ” ...
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... Updated tables in ”Signals Description” on page Updated Table 9-2 on page 77, Table 9-9 on page ”Peripherals” on page 75. Updated module names and abbreviations through the datasheet. Initial revision. AT32AP7002 933 ”Peripherals” on page ”Memories” on page 77. ”Peripheral overview” on page 94. Figure 1-2 on page 1. Table 27-9 on page 523 ...
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... Request Signal Map ..................................................................................21 7.3DMACA Handshake Interface Map .........................................................................22 7.4Clock Connections ...................................................................................................23 7.5External Interrupt Pin Mapping ................................................................................24 7.6Nexus OCD AUX port connections ..........................................................................24 7.7Peripheral Multiplexing on IO lines ..........................................................................25 7.8Peripheral overview .................................................................................................32 8 Boot Sequence ....................................................................................... 38 8.1Starting of clocks .....................................................................................................38 8.2Fetching of initial instructions ..................................................................................38 9 Ordering Information ............................................................................. 39 32054DS–AVR32–10/07 AT32AP7002 i ...
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... Errata ....................................................................................................... 40 10.1Rev. C ....................................................................................................................40 10.2Rev. B ....................................................................................................................46 10.3Rev. A ....................................................................................................................46 11 Datasheet Revision History ................................................................... 47 11.1Rev. D 09/07 ..........................................................................................................47 11.2Rev. C 07/07 ..........................................................................................................48 11.3Rev. B 04/07 ..........................................................................................................48 11.4Rev. A 02/07 ..........................................................................................................48 Table of Contents....................................................................................... i 32054DS–AVR32–10/07 AT32AP7002 ii ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...