at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 386

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

32059J–12/2010
•Control read
USB Bus
RXSTPI
RXOUTI
TXINI
Wr Enable
HOST
Wr Enable
CPU
Figure 22-15. Control Write
Figure 22-16 on page 386
simultaneous write requests from the CPU and the USB host.
Figure 22-16. Control Read
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all the data written by the CPU are lost and clear-
ing TXINI has no effect.
The user checks if the transmission or the reception is complete.
The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the
following software algorithm:
Once the OUT status stage has been received, the USBB waits for a SETUP request. The
SETUP request has priority over any other request and has to be ACKed. This means that any
other bit should be cleared and the FIFO reset when a SETUP is received.
The user has to take care of the fact that the byte counter is reset when a zero-length OUT
packet is received.
USB Bus
RXSTPI
RXOUTI
TXINI
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
SETUP
SETUP
HW
SETUP
SETUP
HW
SW
SW
SW
IN
shows a control read transaction. The USBB has to manage the
HW
OUT
HW
DATA
SW
IN
SW
DATA
OUT
HW
OUT
NAK
SW
STATUS
NAK
IN
AT32UC3B
STATUS
OUT
SW
HW
IN
SW
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