at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 344
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at32uc3b0512-z2ues
Manufacturer Part Number
at32uc3b0512-z2ues
Description
32-bit Avr Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT32UC3B0512-Z2UES.pdf
(680 pages)
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Table 21-15.
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Table 21-16.
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Table 21-17.
32059J–12/2010
CLKO: Clock Output Select
MODE9: 9-bit Character Length
MSBF/CPOL: Bit Order or SPI Clock Polarity
CHMODE: Channel Mode
NBSTOP: Number of Stop Bits
PAR: Parity Type
0
0
1
1
0
0
1
1
0
0
0
0
1
1
CHMODE
NBSTOP
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin if USCLKS does not select the external clock CLK.
0: CHRL defines character length.
1: 9-bit character length.
If USART does not operate in SPI Mode (MODE … 0xE and 0xF):
MSBF = 0: Least Significant Bit is sent/received first.
MSBF = 1: Most Significant Bit is sent/received first.
If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
clock/data relationship between master and slave devices.
PAR
0
1
0
1
0
1
0
1
0
0
1
1
0
1
Mode Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input.
Remote Loopback. RXD pin is internally connected to the TXD pin.
Asynchronous (SYNC = 0)
1 stop bit
1.5 stop bits
2 stop bits
Reserved
0
1
0
1
x
x
Parity Type
Even parity
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
Synchronous (SYNC = 1)
1 stop bit
Reserved
2 stop bits
Reserved
AT32UC3B
344
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