at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 381
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at32uc3b0512-z2ues
Manufacturer Part Number
at32uc3b0512-z2ues
Description
32-bit Avr Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT32UC3B0512-Z2UES.pdf
(680 pages)
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22.7.2
22.7.2.1
22.7.2.2
22.7.2.3
32059J–12/2010
USB Device Operation
Introduction
Power-On and reset
USB reset
In device mode, the USBB supports full- and low-speed data transfers.
In addition to the default control endpoint, six endpoints are provided, which can be configured
with the types isochronous, bulk or interrupt, as described in
The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.
Figure 22-13 on page 381
Figure 22-13. Device Mode States
After a hardware reset, the USBB device mode is in the Reset state. In this state:
• The macro clock is stopped in order to minimize power consumption (FRZCLK is written to
• The internal registers of the device mode are reset.
• The endpoint banks are de-allocated.
• Neither D+ nor D- is pulled up (DETACH is written to one).
D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written
to zero and VBus is present. See
When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode
state goes to the Idle state with minimal power consumption. This does not require the USB
clock to be activated.
The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing
a zero to USBE) or when host mode is engaged (ID is zero).
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
one).
describes the USBB device mode main states.
RESET
HW
| ID = 0
USBE = 0
“Device mode”
Reset
| ID = 0
& ID = 1
USBE = 0
state>
other
<any
USBE = 1
for further details.
Idle
Table 22-1 on page
AT32UC3B
365.
381
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