atmega323l ATMEL Corporation, atmega323l Datasheet - Page 51
atmega323l
Manufacturer Part Number
atmega323l
Description
Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA323L.pdf
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1457G–AVR–09/03
Figure 34. Effects of Unsynchronized OCR Latching in Up/Down Mode
Figure 35. Effects of Unsynchronized OCR Latching in Overflow Mode
Note:
During the time between the write and the latch operation, a read from the Output Com-
pare Registers will read the contents of the temporary location. This means that the
most recently written value always will read out of OCR0 and OCR2.
When the Output Compare Register contains $00 or $FF, and the up/down PWM mode
is selected, the output PB3(OC0/PWM0)/PD7(OC2/PWM2) is updated to low or high on
the next compare match according to the settings of COMn1/COMn0. This is shown in
Table 16. In overflow PWM mode, the output PB3(OC0/PWM0)/PD7(OC2/PWM2) is
held low or high only when the Output Compare Register contains $FF.
Compare Value changes
n = 0 or 2 (Figure 34 and Figure 35).
Compare Value changes
Unsynchronized OCn Latch
Synchronized OCn Latch
Synchronized OCn Latch
Unsynchronized OCn Latch
Compare Value changes
Glitch
Compare Value changes
Glitch
ATmega323(L)
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
Counter Value
Compare Value
PWM Output OCn
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