atmega323l ATMEL Corporation, atmega323l Datasheet - Page 97
atmega323l
Manufacturer Part Number
atmega323l
Description
Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA323L.pdf
(247 pages)
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USART Control and Status
Register C – UCSRC
1457G–AVR–09/03
The UCSRC Register shares the same I/O location as the UBRRH Register. See the
“Accessing UBRRH/UCSRC Registers” on page 92 section which describes how to
access this register.
• Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as
one when reading UCSRC. The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 32. USART Mode
• Bit 5:4 – UPM1:0: Parity Mode
This bit enable and set type of parity generation and check. If enabled, the Transmitter
will automatically generate and send the parity of the transmitted data bits within each
frame. The Receiver will generate a parity value for the incoming data and compare it to
the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set.
Table 33. Parity Mode
• Bit 3 – USBS: Stop Bit Select
This bit selects number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Table 34. Stop Bit Select
Bit
$20 ($40)
Read/Write
Initial Value
USBS
0
1
UMSEL
0
1
UPM1
0
0
1
1
URSEL
Mode
Asynchronous Operation
Synchronous Operation
R/W
7
1
UMSEL
R/W
6
0
UPM0
0
1
0
1
UPM1
R/W
5
0
Stop Bit(s)
1-bit
2-bit
UPM0
R/W
Parity Mode
Disabled
(Reserved)
Enabled, Even Parity
Enabled, Odd Parity
4
0
USBS
R/W
3
0
UCSZ1
R/W
2
1
ATmega323(L)
UCSZ0
R/W
1
1
UCPOL
R/W
0
0
UCSRC
97
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