lm96080cimt National Semiconductor Corporation, lm96080cimt Datasheet - Page 23

• Manufacturer Part Number: lm96080cimt
• Description: System Hardware Monitor With 2-wire Serial Interface
• Manufacturer: National Semiconductor Corporation

Configuration Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Mask Register 1
Interrupt Mask Register 2
Fan Divisor/RST_OUT/OS
OS Configuration/Temperature
Resolution Register
Conversion Rate Register
Channel Disable Register
Value RAM
7-0 Address Pointer
Bit
Bit
0
1
2
3
4
5
6
7
12.0 REGISTERS AND RAM
12.1 Address Register
The bit designations for a register are as follows:
12.2 Address Pointer Index (A7–A0)
12.3 Configuration Register—Address 00h
Power on default <7:0> = 00001000 binary
Start
INT Enable
INT Polarity
Select
INT_Clear
RESET
Chassis Clear
GPO
INITIALIZATION
Bit 7
A7
Registers and RAM
Name
Name
Bit 6
A6
Read/Write Address of RAM and Registers. See the tables below for detail.
Read/Write A one enables startup of monitoring operations, a zero puts the part in shutdown mode.
Read/Write A one enables the INT Interrupt output.
Read/Write A one selects an active high open source output while a zero selects an active low open drain
Read/Write A one disables the INT output without affecting the contents of Interrupt Status Registers. The
Read/Write A one outputs at least a 10 ms active low reset signal at RST_OUT, if bit 7 and bit 6 in the Fan
Read/Write A one clears the GPI (Chassis Intrusion) pin. This bit clears itself after 10 ms.
Read/Write A one drives the GPO (General Purpose Output) pin low.
Read/Write A one restores power on default value to the Configuration Register, Interrupt Status Registers,
Read/Write
Read/Write
Note: Unlike the "INT_Clear" bit, the outputs of Interrupt pins will not be cleared if the user writes
a zero to this location after an interrupt has occurred. At startup, limit checking functions and
scanning begin. Note, all limits should be set in the Value RAM before setting this bit HIGH.
output.
device will stop monitoring. It will resume upon clearing of this bit.
Divisor/RST_OUT/OS Register (address 05h) = 1 and = 0, respectively. This bit is cleared once
the pulse has gone inactive.
Interrupt Mask Registers, Fan Divisor/RST_OUT/OS Register, the OS Configuration/
Temperature Resolution Register, Conversion Rate, Channel Disable, Manufacturers ID and
Stepping/Die revision ID registers. This bit clears itself. The power-on default is zero.
Bit 5
A5
A7–A0 in Hex
Address Pointer (Power On default 00h)
20h – 3Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
Bit 4
A4
23
Bit 3
A3
Description
Description
Register 3Eh defaults to 0000 0001
Register 3Fh defaults to 0000 1000
Power On Value of Registers:
Bit 2
<7:0> in Binary
A2
0000 1000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0100
0000 0001
0000 0000
0000 0000
Bit 1
A1
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Bit 0
A0