lm96080cimt National Semiconductor Corporation, lm96080cimt Datasheet - Page 22

• Manufacturer Part Number: lm96080cimt
• Description: System Hardware Monitor With 2-wire Serial Interface
• Manufacturer: National Semiconductor Corporation

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cleared until the Registers are updated by the monitoring
loop. The INT output pin is cleared with the INT_Clear bit (ad-
dress 00h, bit 3), without affecting the contents of the Interrupt
10.0 RST_OUT and GPO OUTPUTS
In PC applications, the open drain GPO provides a gate drive
signal to an external PMOS power switch. This external MOS-
FET would keep the power turned on regardless of the state
of the front panel power switches when software power con-
trol is used. In any given application, this signal is not limited
to the function described by its label. For example, since the
LM96080 incorporates temperature sensing, the GPO output
could also be utilized to control power to a cooling fan. Take
GPO active low by setting bit 6 in the Configuration Register
(address 00h) high.
RST_OUT is intended to provide a master reset to devices
connected to this line. RST Enable, bit 7 of address 05h, is
the RST_OUT/OS control bit that must be set high to enable
this function. Setting bit 4, RESET, in the Configuration Reg-
ister (address 00h) high outputs a low pulse of at least 10 ms
on this line, at the end of which bit 4 in the Configuration Reg-
ister automatically clears. Again, the label for this pin is only
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Status Registers. When this bit is high, the LM96080 moni-
toring loop will stop and will resume when the bit is low.
its suggested use. In applications where the RST_OUT ca-
pability is not needed, it can be used for any type of digital
control that requires a 10 ms active low open drain output.
11.0 NAND TREE TESTS
A NAND tree is provided in the LM96080 for Automated Test
Equipment (ATE) board level connectivity testing. If the user
applies a logic zero to the NTEST_IN/Reset_IN input pin, the
device will be in the NAND tree test mode. A0/NTEST_OUT
will become the NAND tree output pin. To perform a NAND
tree test, all pins included in the NAND tree should be driven
to 1. Beginning with IN0 and working clockwise around the
chip, each pin can be toggled and a resulting toggle can be
observed on A0/NTEST_OUT. The following pins are exclud-
ed from the NAND tree test: GNDA (analog ground), GND
(digital ground), V
NTEST_IN/Reset_IN and RST_OUT/OS. Allow for a typical
propagation delay of 500 ns.
+
(power supply), A0/NTEST_OUT,