ap1260mp APEC, ap1260mp Datasheet

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ap1260mp

Manufacturer Part Number
ap1260mp
Description
Peak 2.5a Sink/source Bus Termination Regulator
Manufacturer
APEC
Datasheet
1.AP1260MP.pdf (6 pages)
Peak 2.5A Sink/Source Bus Termination Regulator
Description
The AP1260MP is a simple, cost-effective and
high-speed linear regulator designed to generate
termination voltage in double data rate (DDR)
memory system to comply with the JEDEC SSTL_2
and SSTL_18 or other specific interfaces such as
HSTL, SCSI-2 and SCSI-3 etc. devices requirements.
The regulator is capable of actively sinking or sourcing
up to 2.5A transient peak current while regulating an
output voltage to within 40mV. The output termination
voltage can be tightly regulated to track 1/2VDDQ by
two external voltage divider resistors or the desired
output voltage can be programmed by externally
forcing the REFEN pin voltage.
The AP1260MP also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely
low initial offset voltage, excellent load regulation,
current limiting in bi-directions and on-chip thermal
shut-down protection.
The AP1260MP are available in the ESOP-8
(Exposed Pad) surface mount packages.
Pin Configuration
Pin Description
V
GND
V
REFEN
V
Pin Name
IN
CNTL
OUT
REFEN
VOUT
GND
VIN
Advanced Power
Electronics Corp.
Power Input
Ground
Gate Drive Voltage
Reference Voltage input and Chip Enable
Output Voltage
ESOP-8 (MP)
1
2
3
4
(Top View)
GND
Pin function
8
7
6
5
NC
NC
VCNTL
NC
Features
Application
Block Diagram
Ideal for DDR-I, DDR-II and DDR-III V
Sink and Source peak 2.5A for DDRI, DDRII and
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL
_18, HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in ESOP-8 (Exposed Pad) Packages
V
100% Lead (Pb)-Free
DDRIII.
IN
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II & DDRIII Memory Systems
and V
CNTL
No Power Sequence Issue
AP1260MP
TT
Applications
200811123
1

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ap1260mp Summary of contents

Page 1

... Advanced Power Electronics Corp. Peak 2.5A Sink/Source Bus Termination Regulator Description The AP1260MP is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. ...

Page 2

... I = -2A OUT I LIM T 3.3V ≤ CNTL ΔT 3.3V ≤ CNTL V Enable IH V Shutdown IL subtracted from V OUT REFEN subtracted from V . OUT REFEN AP1260MP Value Unit -65 to 150 °C 260 °C 28 ºC/W Units V V ℃ ℃ Min Typ Max -- 1 -- ...

Page 3

... Advanced Power Electronics Corp. Peak 2.5A Sink/Source Bus Termination Regulator Typical Operating Characteristics AP1260MP 3 ...

Page 4

... Peak 2.5A Sink/Source Bus Termination Regulator Application Information Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the AP1260MP. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. ...

Page 5

... 10µF (Ceramic) + 1000µF under the worst case testing condition OUT, min R = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present DUMMY C = 1µ 470µF(Low ESR 47µF CNTL AP1260MP 5 ...

Page 6

Package Outline : ESOP Part Marking Information & Packing : ESOP-8 1260MP YWWSSS ADVANCED POWER ELECTRONICS CORP Part Number Package Code Date Code (YWWSSS) Y：Last Digit Of The Year WW：Week SSS：Sequence Millimeters SYMBOLS ...

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